skip to main content
research-article

Optimizing FPGA Performance, Power, and Dependability with Linear Programming

Authors Info & Claims
Published:29 June 2017Publication History
Skip Abstract Section

Abstract

Field-programmable gate arrays (FPGA) are an increasingly attractive alternative to traditional microprocessor-based computing architectures in extreme-computing domains, such as aerospace and supercomputing. FPGAs offer several resource types that offer different tradeoffs between speed, power, and area, which make FPGAs highly flexible for varying application computational requirements. However, since an application’s computational operations can map to different resource types, a major challenge in leveraging resource-diverse FPGAs is determining the optimal distribution of these operations across the device’s available resources for varying FPGA devices, resulting in an extremely large design space. In order to facilitate fast design-space exploration, this article presents a method based on linear programming (LP) that determines the optimal operation distribution for a particular device and application with respect to performance, power, or dependability metrics. Our LP method is an effective tool for exploring early designs by quickly analyzing thousands of FPGAs to determine the best FPGA devices and operation distributions, which significantly reduces design time. We demonstrate our LP method’s effectiveness with two case studies involving dot-product and distance-calculation kernels on a range of Virtex-5 FPGAs. Results show that our LP method selects optimal distributions of operations to within an average of 4% of actual values.

References

  1. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss. 1999. Digital circuit design for minimum transient energy and a linear programming method. In Proceedings of the Twelfth International Conference on VLSI Design. 434--439. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. R. G. Bland. 1977. New finite pivoting rules for the simplex method. Math. Operat. Res. 2, 2 (1977), 103--107. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. C. L. Cole and J. L. Crassidis. 2006. Fast star-pattern recognition using planar triangles. J. Guid. Contr. Dynam. 29, 64--71.Google ScholarGoogle ScholarCross RefCross Ref
  4. R. Enzler, T. Jeger, D. Cottet, and G. Tröster. 2000. Proceedings of the 10th International Conference on Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL’00). Springer Berlin. 525--534.Google ScholarGoogle Scholar
  5. M. Flynn and P. Hung. 2005. Microprocessor design issues: Thoughts on the road ahead. IEEE Micro. 25, 3, 16--31. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. A. George, H. Lam, and G. Stitt. 2011. Novo-G: At the forefront of scalable reconfigurable supercomputing. Comput. Sci. Eng. 13, 1 (2011), 82--86. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Z. Guo, W. Najjar, F. Vahid, and K. Vissers. 2004. A quantitative analysis of the speedup factors of FPGAs over processors. In Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA’04). ACM, New York. 162--170. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. D. M. Hiemstra, G. Battiston, and P. Gill. 2010. Single event upset characterization of the virtex-5 field programmable gate array using proton irradiation. In Proceedings of the 2010 IEEE Radiation Effects Data Workshop (REDW’10). 1--4.Google ScholarGoogle Scholar
  9. B. Holland, K. Nagarajan, and A. D. George. 2009. RAT: RC amenability test for rapid performance prediction. ACM Trans. Reconfig. Technol. Syst. 1, 4, Article 22. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein. 2005. Scaling, power, and the future of CMOS. In Proceedings of the IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. 7--15.Google ScholarGoogle Scholar
  11. H. Iwai. 2015. Future of nano {CMOS} technology. Solid-State Electron. 112 (2015), 56--67.Google ScholarGoogle ScholarCross RefCross Ref
  12. D. L. Landis, J. R. Samson, and J. H. Aldridge. 1990. Defect and Fault Tolerance in VLSI Systems: Volume 2. Springer, Boston, MA. 267--281.Google ScholarGoogle Scholar
  13. N. R. Mahapatra and B. Venkatrao. 1999. The processor-memory bottleneck: Problems and solutions. Crossroads 5, 3, Article 2. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. M. R. Meswani, L. Carrington, D. Unat, A. Snavely, S. Baden, and S. Poole. 2012. Modeling and predicting performance of high performance computing applications on hardware accelerators. In Proceedings of the IEEE 26th International Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW’12). 1828--1837. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. D. Petrick, A. Geist, D. Albaijes, M. Davis, P. Sparacino, G. Crum, R. Ripley, J. Boblitt, and T. Flatley. 2014. SpaceCube v2.0 space flight hybrid reconfigurable data processing system. In Proceedings of the 2014 IEEE Aerospace Conference. 1--20.Google ScholarGoogle Scholar
  16. A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Y. Xiao, and D. Burger. 2014. A reconfigurable fabric for accelerating large-scale datacenter services. In Proceedings of the 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA’14). 13--24. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. H. Quinn, K. Morgan, P. Graham, J. Krone, and M. Caffrey. 2007. Static proton and heavy ion testing of the Xilinx virtex-5 device. In Proceedings of the IEEE Radiation Effects Data Workshop. 177--184.Google ScholarGoogle Scholar
  18. J. W. Richardson, A. D. George, and H. Lam. 2012. Performance analysis of GPU accelerators with realizable utilization of computational density. In Proceedings of the 2012 Symposium on Application Accelerators in High Performance Computing (SAAHPC’12). 137--140. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. D. Rudolph, C. Wilson, J. Stewart, P. Gauvin, G. Crum, A. D. George, M. Wirthlin, and H. Lam. 2014. CSP: A multifaceted hybrid system for space computing. In Proceedings of the 28th Annual AIAA/USU Conference on Small Satellites. 1--7.Google ScholarGoogle Scholar
  20. K. Srinivasan, K. S. Chatha, and G. Konjevod. 2006. Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14, 4, 407--420. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. A. J. Tylka, J. H. Adams, P. R. Boberg, B. Brownstein, W. F. Dietrich, E. O. Flueckiger, E. L. Petersen, M. A. Shea, D. F. Smart, and E.C. Smith. 1997. CREME96: A revision of the cosmic ray effects on micro-electronics code. IEEE Trans. Nucl. Sci. 44, 6, 2150--2160.Google ScholarGoogle ScholarCross RefCross Ref
  22. K. Underwood. 2004. FPGAs vs. CPUs: Trends in peak floating-point performance. In Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA’04). ACM, New York. 171--180. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. R. J. Vanderbei. 2001. Linear Programming: Foundations and Extensions. Springer.Google ScholarGoogle ScholarCross RefCross Ref
  24. J. Williams, A. D. George, J. Richardson, K. Gosrani, C. Massie, and H. Lam. 2010. Characterization of fixed and reconfigurable multi-core devices for application acceleration. ACM Trans. Reconfig. Technol. Syst. 3, 4, 19:1--19:29. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Optimizing FPGA Performance, Power, and Dependability with Linear Programming

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        • Published in

          cover image ACM Transactions on Reconfigurable Technology and Systems
          ACM Transactions on Reconfigurable Technology and Systems  Volume 10, Issue 3
          September 2017
          187 pages
          ISSN:1936-7406
          EISSN:1936-7414
          DOI:10.1145/3102109
          • Editor:
          • Steve Wilton
          Issue’s Table of Contents

          Copyright © 2017 ACM

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 29 June 2017
          • Accepted: 1 February 2017
          • Revised: 1 December 2016
          • Received: 1 April 2016
          Published in trets Volume 10, Issue 3

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • research-article
          • Research
          • Refereed

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader
        About Cookies On This Site

        We use cookies to ensure that we give you the best experience on our website.

        Learn more

        Got it!