Abstract
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the design and placement of different components in the DRAM chip: different regions in DRAM, based on their relative distances from the peripheral structures, require different minimum access latencies for reliable operation. In particular, we show that in most real DRAM chips, cells closer to the peripheral structures can be accessed much faster than cells that are farther. We call this phenomenon design-induced variation in DRAM. Our goals are to i) understand design-induced variation that exists in real, state-of-the-art DRAM chips, ii) exploit it to develop low-cost mechanisms that can dynamically find and use the lowest latency at which to operate a DRAM chip reliably, and, thus, iii) improve overall system performance while ensuring reliable system operation.
To this end, we first experimentally demonstrate and analyze designed-induced variation in modern DRAM devices by testing and characterizing 96 DIMMs (768 DRAM chips). Our characterization identifies DRAM regions that are vulnerable to errors, if operated at lower latency, and finds consistency in their locations across a given DRAM chip generation, due to design-induced variation. Based on our extensive experimental analysis, we develop two mechanisms that reliably reduce DRAM latency. First, DIVA Profiling uses runtime profiling to dynamically identify the lowest DRAM latency that does not introduce failures. DIVA Profiling exploits design-induced variation and periodically profiles only the vulnerable regions to determine the lowest DRAM latency at low cost. It is the first mechanism to dynamically determine the lowest latency that can be used to operate DRAM reliably. DIVA Profiling reduces the latency of read/write requests by 35.1%/57.8%, respectively, at 55°C. Our second mechanism, DIVA Shuffling, shuffles data such that values stored in vulnerable regions are mapped to multiple error-correcting code (ECC) codewords. As a result, DIVA Shuffling can correct 26% more multi-bit errors than conventional ECC. Combined together, our two mechanisms reduce read/write latency by 40.0%/60.5%, which translates to an overall system performance improvement of 14.7%/13.7%/13.8% (in 2-/4-/8-core systems) across a variety of workloads, while ensuring reliable operation.
- DIVA-DRAM Simulation Model and Experimental Data. https://github.com/Carnegie Mellon University-SAFARI/DIVA-DRAM.Google Scholar
- Ramulator. https://github.com/Carnegie Mellon University-SAFARI/ramulator.Google Scholar
- J. Ahn, S. Hong, S. Yoo, O. Mutlu, and K. Choi. A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. In ISCA, 2015. Google Scholar
Digital Library
- J. Ahn, S. Yoo, O. Mutlu, and K. Choi. PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture. In ISCA, 2015. Google Scholar
Digital Library
- A. Ailamaki, D. J. DeWitt, M. D. Hill, and D. A. Wood. DBMSs on a Modern Processor: Where Does Time Go? In VLDB, 1999. Google Scholar
Digital Library
- A. R. Alameldeen, I. Wagner, Z. Chishti, W. Wu, C. Wilkerson, and S.-L. Lu. Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes. In ISCA, 2011. Google Scholar
Digital Library
- Arizona State Univ. Predictive Technology Model. http://ptm.asu.edu/, 2012.Google Scholar
- K. Arndt, C. Narayan, A. Brintzinger, W. Guthrie, D. Lachtrupp, J. Mauger, D. Glimmer, S. Lawn, B. Dinkel, and A. Mitwalsky. Reliability of Laser Activated Metal Fuses in DRAMs. In IEMT, 1999.Google Scholar
Cross Ref
- S. Borkar and A. A. Chien. The Future of Microprocessors. In CACM, 2011. Google Scholar
Digital Library
- A. Boroumand, S. Ghose, B. Lucia, K. Hsieh, K. Malladi, H. Zheng, and O. Mutlu. LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory. In IEEE CAL, 2016.Google Scholar
- S. Cha, S. O, H. Shin, S. Hwang, K. Park, S. Jang, J. Choi, G. Jin, Y. Son, H. Cho, J. Ahn, and N. Kim. Defect Analysis and Cost Effective Resilience Architecture for Future DRAM Devices. In HPCA, 2017.Google Scholar
Cross Ref
- K. Chandrasekar, S. Goossens, C. Weis, M. Koedam, B. Akesson, N. Wehn, and K. Goossens. Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization. In DATE, 2014. Google Scholar
Digital Library
- K. K. Chang. Understanding and Improving Latency of DRAM-Based Memory Systems. PhD thesis, Carnegie Mellon University, 2017.Google Scholar
- K. K. Chang, A. Kashyap, H. Hassan, S. Ghose, K. Hsieh, D. Lee, T. Li, G. Pekhimenko, S. Khan, and O. Mutlu. Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization. In SIGMETRICS, 2016. Google Scholar
Digital Library
- K. K. Chang, D. Lee, Z. Chishti, A. Alameldeen, C. Wilkerson, Y. Kim, and O. Mutlu. Improving DRAM Performance by Parallelizing Refreshes with Accesses. In HPCA, 2014.Google Scholar
Cross Ref
- K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, and O. Mutlu. Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM. In HPCA, 2016.Google Scholar
Cross Ref
- K. K. Chang, A. G. Yaglikci, A. Agrawal, N. Chatterjee, S. Ghose, A. Kashyap, H. Hassan, D. Lee, M. O'Connor, and O. Mutlu. Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. In SIGMETRICS, 2017. Google Scholar
Digital Library
- C. Elm, M. Klein, and D. Tavangarian. Automatic On-Line Memory Tests in Workstations. In MTDT, 1994.Google Scholar
Cross Ref
- S. Eyerman and L. Eeckhout. System-Level Performance Metrics for Multiprogram Workloads. In IEEE Micro, 2008. Google Scholar
Digital Library
- A. Farmahini-Farahani, J. H. Ahn, K. Morrow, and N. S. Kim. NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules. In HPCA, 2015.Google Scholar
Cross Ref
- M. Gao, G. Ayers, and C. Kozyrakis. Practical Near-Data Processing for In-Memory Analytics Frameworks. In PACT, 2015. Google Scholar
Digital Library
- Q. Guo, N. Alachiotis, B. Akin, F. Sadi, G. Xu, T. M. Low, L. Pileggi, J. C. Hoe, and F. Franchetti. 3D Stacked Memory-Side Acceleration: Accelerator and System Design. In WoNDP, 2014.Google Scholar
- H. Hassan, G. Pekhimenko, N. Vijaykumar, V. Seshadri, D. Lee, O. Ergin, and O. Mutlu. ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality. In HPCA, 2016Google Scholar
Cross Ref
- H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhimenko, D. Lee, O. Ergin, and O. Mutlu. SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies. In HPCA, 2017.Google Scholar
Cross Ref
- M. Horiguchi and K. Itoh. Nanoscale Memory Repair. Springer, 2013. Google Scholar
Digital Library
- HPC Challenge. GUPS. http://icl.cs.utk.edu/projectsfiles/hpcc/RandomAccess/.Google Scholar
- K. Hsieh, E. Ebrahimi, G. Kim, N. Chatterjee, M. O'Connor, N. Vijaykumar, O. Mutlu, and S. W. Keckler. Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems. In ISCA, 2016. Google Scholar
Digital Library
- K. Hsieh, S. Khan, N. Vijaykumar, K. K. Chang, A. Boroumand, S. Ghose, and O. Mutlu. Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation. In ICCD, 2016.Google Scholar
Cross Ref
- A. A. Hwang, I. A. Stefanovici, and B. Schroeder. Cosmic Rays Don't Strike Twice: Understanding the Nature of DRAM Errors and the Implications for System Design. In ASPLOS, 2012. Google Scholar
Digital Library
- M. Inoue, T. Yamada, H. Kotani, H. Yamauchi, A. Fujiwara, J. Matsushima, H. Akamatsu, M. Fukumoto, M. Kubota, I. Nakao, N. Aoi, G. Fuse, S. Ogawa, S. Odanaka, A. Ueno, and H. Yamamoto. A 16-Mbit DRAM with a Relaxed Sense Amplifier-Pitch Open-Bit-Line Architecture. In JSSC, 1988.Google Scholar
Cross Ref
- JEDEC Solid State Technology Assn. JESD79--3F: DDR3 SDRAM Standard, 2012.Google Scholar
- T. S. Jung. Memory technology and solutions roadmap. http://www.sec.co.kr/images/corp/ir/irevent/techforum_01.pdf, 2005.Google Scholar
- U. Kang, H.-S. Yu, C. Park, H. Zheng, J. Halbert, K. Bains, S. Jang, and J. Choi. Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling. In The Memory Forum, 2014.Google Scholar
- B. Keeth, R. J. Baker, B. Johnson, and F. Lin. DRAM Circuit Design: Fundamental and High-Speed Topics. Wiley-IEEE Press, 2007. Google Scholar
Digital Library
- S. Khan, D. Lee, Y. Kim, A. R. Alameldeen, C. Wilkerson, and O. Mutlu. The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study. In SIGMETRICS, 2014. Google Scholar
Digital Library
- S. Khan, D. Lee, and O. Mutlu. PARBOR: An Efficient System-Level Technique to Detect Data Dependent Failures in DRAM. In DSN, 2016.Google Scholar
Cross Ref
- S. Khan, C. Wilkerson, D. Lee, A. R. Alameldeen, and O. Mutlu. A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM. In IEEE CAL, 2016.Google Scholar
- J. Kim, M. Sullivan, and M. Erez. Bamboo ECC: Strong, Safe, and Flexible Codes for Reliable Computer Memory. In HPCA, 2015.Google Scholar
Cross Ref
- K. Kim and J. Lee. A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs. In EDL, 2009.Google Scholar
Cross Ref
- Y. Kim. Architectural Techniques to Enhance DRAM Scaling. PhD thesis, Carnegie Mellon University, 2015.Google Scholar
- Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA, 2014. Google Scholar
Digital Library
- Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu. A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM. In ISCA, 2012. Google Scholar
Digital Library
- Y. Kim, W. Yang, and O. Mutlu. Ramulator: A Fast and Extensible DRAM Simulator. In IEEE CAL, 2015. Google Scholar
Digital Library
- O. Kocberber, B. Grot, J. Picorel, B. Falsafi, K. Lim, and P. Ranganathan. Meet the Walkers: Accelerating Index Traversals for In-Memory Databases. In MICRO, 2013. Google Scholar
Digital Library
- P. M. Kogge. EXECUBE-A New Architecture for Scaleable MPPs. In ICPP, 1994. Google Scholar
Digital Library
- D. Lee. Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity. PhD thesis, Carnegie Mellon University, 2016.Google Scholar
- D. Lee, S. M. Khan, L. Subramanian, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, S. Ghose, and O. Mutlu. Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips. In CoRR abs/1610.09604, 2016. Google Scholar
Digital Library
- D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu. Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case. In HPCA, 2015.Google Scholar
Cross Ref
- D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, and O. Mutlu. Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture. In HPCA, 2013. Google Scholar
Digital Library
- D. Lee, L. Subramanian, R. Ausavarungnirun, J. Choi, and O. Mutlu. Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM. In PACT, 2015. Google Scholar
Digital Library
- X. Li, K. Shen, M. C. Huang, and L. Chu. A Memory Soft Error Measurement on Production Systems. In USENIX ATC, 2007. Google Scholar
Digital Library
- J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, and O. Mutlu. An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms. In ISCA, 2013. Google Scholar
Digital Library
- J. Liu, B. Jaiyen, R. Veras, and O. Mutlu. RAIDR: Retention-Aware Intelligent DRAM Refresh. In ISCA, 2012. Google Scholar
Digital Library
- C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In PLDI, 2005. Google Scholar
Digital Library
- Y. Luo, S. Govindan, B. Sharma, M. Santaniello, J. Meza, A. Kansal, J. Liu, B. Khessib, K. Vaid, and O. Mutlu. Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory. In DSN, 2014. Google Scholar
Digital Library
- J. D. McCalpin. STREAM Benchmark. http://www.streambench.org/.Google Scholar
- J. Meza, Q. Wu, S. Kumar, and O. Mutlu. Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field. In DSN, 2015. Google Scholar
Digital Library
- Micron Technology, Inc. RLDRAM 2 and 3 Specifications. http://www.micron.com/products/dram/rldram-memGoogle Scholar
- Micron Technology, Inc. 4Gb DDR3 SDRAM (MT41J512M8), 2012.Google Scholar
- K.-S. Min, J.-T. Park, S.-P. Lee, Y.-H. Kim, T.-H. Yang, J.-D. Joo, K.-M. Lee, J.-K. Wee, and J.-Y. Chung. A Post-Package Bit-Repair Scheme Using Static Latches with Bipolar-Voltage Programmable Antifuse Circuit for High-Density DRAMs. In VLSI, 2001.Google Scholar
- N. S. Mirzadeh, O. Kocberber, B. Falsafi, and B. Grot. Sort vs. Hash Join Revisited for Near-Memory Execution. In ASBD, 2015.Google Scholar
- Y. Mori, K. Ohyu, K. Okonogi, and R.-I. Yamada. The Origin of Variable Retention Time in DRAM. In IEDM, 2005.Google Scholar
Cross Ref
- T. Moscibroda and O. Mutlu. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems. In USENIX Security, 2007. Google Scholar
Digital Library
- O. Mutlu. Memory Scaling: A Systems Architecture Perspective. In IMW, 2013.Google Scholar
- O. Mutlu. The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser. In DATE, 2017.Google Scholar
Digital Library
- O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. In HPCA, 2003. Google Scholar
Digital Library
- O. Mutlu and L. Subramanian. Research Problems and Opportunities in Memory Systems. In SUPERFRI, 2014. Google Scholar
Digital Library
- P. J. Nair, D.-H. Kim, and M. K. Qureshi. ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error Rates. In ISCA, 2013. Google Scholar
Digital Library
- M. Patel, J. Kim, and O. Mutlu. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions. In ISCA, 2017. Google Scholar
Digital Library
- H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi. Pinpointing Representative Portions of Large Intel Itanium Programs with Dynamic Instrumentation. In MICRO, 2004. Google Scholar
Digital Library
- D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick. A Case for Intelligent RAM. In IEEE Micro, 1997. Google Scholar
Digital Library
- D. A. Patterson. Latency Lags Bandwidth. In CACM, 2004. Google Scholar
Digital Library
- A. Pattnaik, X. Tang, A. Jog, O. Kayiran, A. K. Mishra, M. T. Kandemir, O. Mutlu, and C. R. Das. Scheduling Techniques for GPU Architectures with Processing-in-Memory Capabilities. In PACT, 2016. Google Scholar
Digital Library
- M. Qureshi, D.-H. Kim, S. Khan, P. Nair, and O. Mutlu. AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems. In DSN, 2015. Google Scholar
Digital Library
- M. Rahman, B. Childers, and S. Cho. COMeT: Continuous Online Memory Test. In PRDC, 2011. Google Scholar
Digital Library
- P. J. Restle, J. W. Park, and B. F. Lloyd. DRAM Variable Retention Time. In IEDM, 1992.Google Scholar
Cross Ref
- S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory Access Scheduling. In ISCA, 2000. Google Scholar
Digital Library
- B. Schroeder and G. Gibson. A Large-Scale Study of Failures in High-Performance Computing Systems. In TDSC, 2010. Google Scholar
Digital Library
- B. Schroeder, E. Pinheiro, and W.-D. Weber. DRAM Errors in the Wild: A Large-Scale Field Study. In SIGMETRICS, 2009. Google Scholar
Digital Library
- V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M. Kozuch, O. Mutlu, P. Gibbons, and T. Mowry. Fast Bulk Bitwise AND and OR in DRAM. In IEEE CAL, 2015. Google Scholar
Digital Library
- V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry. RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization. In MICRO, 2013. Google Scholar
Digital Library
- V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry. Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM. In CoRR abs/1605.06483, 2016.Google Scholar
- V. Seshadri, T. Mullins, A. Boroumand, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry. Gather Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-Unit Strided Accesses. In MICRO, 2015. Google Scholar
Digital Library
- W. Shin, J. Yang, J. Choi, and L.-S. Kim. NUAT: A Non-Uniform Access Time Memory Controller. In HPCA, 2014.Google Scholar
Cross Ref
- A. Singh, D. Bose, and S. Darisala. Software Based In-System Memory Test for Highly Available Systems. In MTDT, 2005. Google Scholar
Digital Library
- A. Snavely and D. M. Tullsen. Symbiotic Jobscheduling for a Simultaneous Multithreaded Processor. In ASPLOS, 2000. Google Scholar
Digital Library
- Y. H. Son, O. Seongil, Y. Ro, J. W. Lee, and J. H. Ahn. Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations. In ISCA, 2013. Google Scholar
Digital Library
- V. Sridharan and D. Liberty. A Study of DRAM Failures in the Field. In SC, 2012. Google Scholar
Digital Library
- V. Sridharan, J. Stearley, N. DeBardeleben, S. Blanchard, and S. Gurumurthi. Feng Shui of Supercomputer Memory: Positional Effects in DRAM and SRAM Faults. In SC, 2013. Google Scholar
Digital Library
- Standard Performance Evaluation Corp. SPEC CPU2006. http://www.spec.org/cpu2006.Google Scholar
- H. S. Stone. A Logic-in-Memory Computer. In IEEE TC, 1970. Google Scholar
Digital Library
- A. Tanabe, T. Takeshima, H. Koike, Y. Aimoto, M. Takada, T. Ishijima, N. Kasai, H. Hada, K. Shibahara, T. Kunio, T. Tanigawa, T. Saeki, M. Sakao, H. Miyamoto, H. Nozue, S. Ohya, T. Murotani, K. Koyama, and T. Okuda. A 30-ns 64-Mb DRAM with Built-In Self-Test and Self-Repair Function. In JSSC, 1992.Google Scholar
Cross Ref
- Transaction Processing Performance Council. TPC Benchmark. http://www.tpc.org/.Google Scholar
- A. J. van de Goor and I. Schanstra. Address and Data Scrambling: Causes and Impact on Memory Tests. In DELTA, 2002. Google Scholar
Digital Library
- R. Venkatesan, S. Herr, and E. Rotenberg. Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM. HPCA, 2006.Google Scholar
Cross Ref
- T. Vogelsang. Understanding the Energy Consumption of Dynamic Random Access Memories. In MICRO, 2010. Google Scholar
Digital Library
- J.-K. Wee, W. Yang, E.-K. Ryou, J.-S. Choi, S.-H. Ahn, J.-Y. Chung, and S.-C. Kim. An Antifuse EPROM Circuitry Scheme for Field- Programmable Repair in DRAM. In JSSC, 2000.Google Scholar
- C. Wilkerson, A. R. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, and S.-L. Lu. Reducing Cache Power with Low-Cost, Multi-Bit Error-Correcting Codes. In ISCA, 2010. Google Scholar
Digital Library
- Xilinx, Inc. Virtex-6 FPGA Integrated Block for PCI Express, 2011. http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf .Google Scholar
- Xilinx, Inc. ML605 Hardware User Guide, 2012. http://www.xilinx.com/support/documentation/boards_and_kits/ug534.pdf .Google Scholar
- Xilinx, Inc. Virtex-6 FPGA Memory Interface Solutions, 2013. http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf .Google Scholar
- D. Yaney, C. Y. Lu, R. Kohler, M. J. Kelly, and J. Nelson. A Meta-Stable Leakage Phenomenon in DRAM Charge Storage - Variable Hold Time. In IEDM, 1987.Google Scholar
- W. Zhao and Y. Cao. New Generation of Predictive Technology Model for Sub-45nm Design Exploration. In ISQED, 2006. Google Scholar
Digital Library
- W. K. Zuravleff and T. Robinson. Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order. U.S. Patent No. 5630096, 1997Google Scholar
Index Terms
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
Recommendations
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
SIGMETRICS '16: Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer ScienceLong DRAM latency is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses;...
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
Performance evaluation reviewVariation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation. We empirically demonstrate a new form of ...
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms
SIGMETRICS '17 Abstracts: Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer SystemsVariation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation. We empirically demonstrate a new form of ...






Comments