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DudeTM: Building Durable Transactions with Decoupling for Persistent Memory

Published:04 April 2017Publication History
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Abstract

Emerging non-volatile memory (NVM) offers non-volatility, byte-addressability and fast access at the same time. To make the best use of these properties, it has been shown by empirical evidence that programs should access NVM directly through CPU load and store instructions, so that the overhead of a traditional file system or database can be avoided. Thus, durable transactions become a common choice of applications for accessing persistent memory data in a crash consistent manner. However, existing durable transaction systems employ either undo logging, which requires a fence for every memory write, or redo logging, which requires intercepting all memory reads within transactions.

This paper presents DUDETM, a crash-consistent durable transaction system that avoids the drawbacks of both undo logging and redo logging. DUDETM uses shadow DRAM to decouple the execution of a durable transaction into three fully asynchronous steps. The advantage is that only minimal fences and no memory read instrumentation are required. This design also enables an out-of-the-box transactional memory (TM) to be used as an independent component in our system. The evaluation results show that DUDETM adds durability to a TM system with only 7.4 ~ 24.6% throughput degradation. Compared to the existing durable transaction systems, DUDETM provides 1.7times to 4.4times higher throughput. Moreover, DUDETM can be implemented with existing hardware TMs with minor hardware modifications, leading to a further 1.7times speedup.

References

  1. Akinaga, H., and Shima, H. Resistive random access memory (ReRAM) based on metal oxides. Proc. IEEE 98, 12 (2010). Google ScholarGoogle ScholarCross RefCross Ref
  2. Apalkov, D., Khvalkovskiy, A., Watts, S., Nikitin, V., Tang, X., Lottis, D., Moon, K., Luo, X., Chen, E., Ong, A., Driskill-Smith, A., and Krounbi, M. Spin-transfer torque magnetic random access memory (STT-MRAM). ACM J. Emerg. Technol. Comput. Syst. 9, 2 (May 2013), 13:1--13:35.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Arulraj, J., Pavlo, A., and Dulloor, S. R. Let's talk about storage & recovery methods for non-volatile memory database systems. In Proceedings of the 2015 ACM SIGMOD International Conference on Management of Data (2015), SIGMOD '15, pp. 707--722. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Atikoglu, B., Xu, Y., Frachtenberg, E., Jiang, S., and Paleczny, M. Workload analysis of a large-scale key-value store. In Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems (2012), SIGMETRICS '12, pp. 53--64. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Atwood, G. Current and emerging memory technology landscape. Flash memory summit (2011), 9--11.Google ScholarGoogle Scholar
  6. Belay, A., Bittau, A., Mashtizadeh, A., Terei, D., Mazières, D., and Kozyrakis, C. Dune: Safe user-level access to privileged CPU features. In Proceedings of the 10th USENIX Conference on Operating Systems Design and Implementation (2012), OSDI '12, pp. 335--348. https://github.com/ix-project/dune.Google ScholarGoogle Scholar
  7. Chatzistergiou, A., Cintra, M., and Viglas, S. D. Rewind: Recovery write-ahead system for in-memory non-volatile data-structures. Proceedings of the VLDB Endowment 8, 5 (2015), 497--508. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Chen, S., Gibbons, P. B., and Nath, S. Rethinking database algorithms for phase change memory. In Proceedings of the Fifth Biennial Conference on Innovative Data Systems Research (Jan. 2011), CIDR '11, pp. 21--31.Google ScholarGoogle Scholar
  9. Chi, P., Lee, W.-C., and Xie, Y. Making B+-tree efficient in PCM-based main memory. In Proceedings of the 2014 International Symposium on Low Power Electronics and Design (2014), ISLPED '14, pp. 69--74. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Coburn, J., Caulfield, A. M., Akel, A., Grupp, L. M., Gupta, R. K., Jhala, R., and Swanson, S. NV-Heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems (2011), ASPLOS XVI, pp. 105--118. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Collet, Y. Lz4: Extremely fast compression algorithm. https://github.com/lz4/lz4, 2013.Google ScholarGoogle Scholar
  12. Cooper, B. F., Silberstein, A., Tam, E., Ramakrishnan, R., and Sears, R. Benchmarking cloud serving systems with YCSB. In Proceedings of the 1st ACM Symposium on Cloud Computing (2010), SoCC '10, pp. 143--154. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Cunha, C., Bestavros, A., and Crovella, M. Characteristics of WWW client-based traces. Tech. rep., BU-CS-95-010, Computer Science Department, Boston University, 1995.Google ScholarGoogle Scholar
  14. Dragojević, A., Narayanan, D., Nightingale, E. B., Renzelmann, M., Shamis, A., Badam, A., and Castro, M. No compromises: Distributed transactions with consistency, availability, and performance. In Proceedings of the 25th Symposium on Operating Systems Principles (2015), SOSP '15, pp. 54--70. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Eilert, S., Leinwander, M., and Crisenza, G. Phase change memory: A new memory enables new memory usage models. In 2009 IEEE International Memory Workshop (May 2009), pp. 1--2. Google ScholarGoogle ScholarCross RefCross Ref
  16. Felber, P., Fetzer, C., Marlier, P., and Riegel, T. Time-based software transactional memory. IEEE Transactions on Parallel and Distributed Systems 21, 12 (2010), 1793--1807. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Felber, P., Fetzer, C., and Riegel, T. Dynamic performance tuning of word-based software transactional memory. In Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (2008), PPoPP '08, pp. 237--246. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Freitas, R. F., and Wilcke, W. W. Storage-class memory: The next storage system technology. IBM Journal of Research and Development 52, 4/5 (2008), 439.Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Giles, E. R., Doshi, K., and Varman, P. SoftWrAP: A lightweight framework for transactional support of storage class memory. In 2015 31st Symposium on Mass Storage Systems and Technologies (MSST) (May 2015), pp. 1--14. Google ScholarGoogle ScholarCross RefCross Ref
  20. Haerder, T., and Reuter, A. Principles of transaction-oriented database recovery. ACM Computing Surveys (CSUR) 15, 4 (1983), 287--317. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Herlihy, M., and Moss, J. E. B. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture (1993), ISCA '93, pp. 289--300. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Intel. NVM Library . https://github.com/pmem/nvml.Google ScholarGoogle Scholar
  23. Intel. Architecture instruction set extensions programming reference, Feb. 2012.Google ScholarGoogle Scholar
  24. Intel, and Micron. Intel and Micron produce breakthrough memory technology, 2015. https://newsroom.intel.com/news-releases/intel-and-micron-produce-breakthrough-memory.Google ScholarGoogle Scholar
  25. International Technology Roadmap for Semiconductors (ITRS). Process, integration, devices and structures. http://www.itrs.net/Links/2011ITRS/2011Chapters/2011PIDS.pdf, 2011.Google ScholarGoogle Scholar
  26. Johnson, R., Pandis, I., Stoica, R., Athanassoulis, M., and Ailamaki, A. Aether: A scalable approach to logging. Proc. VLDB Endow. 3, 1-2 (Sept. 2010), 681--692. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Kimura, H. FOEDUS: OLTP engine for a thousand cores and NVRAM. In Proceedings of the 2015 ACM SIGMOD International Conference on Management of Data (2015), SIGMOD '15, pp. 691--706. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Kolli, A., Pelley, S., Saidi, A., Chen, P. M., and Wenisch, T. F. High-performance transactions for persistent memories. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems (2016), ASPLOS '16, pp. 399--411. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Kültürsay, E., Kandemir, M., Sivasubramaniam, A., and Mutlu, O. Evaluating STT-RAM as an energy-efficient main memory alternative. In Proceeding of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software (Apr. 2013), ISPASS '13, pp. 256--267. Google ScholarGoogle ScholarCross RefCross Ref
  30. Lee, B., Zhou, P., Yang, J., Zhang, Y., Zhao, B., Ipek, E., Mutlu, O., and Burger, D. Phase-change technology and the future of main memory. IEEE Micro 30 (Jan. 2010), 131--141. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Lim, H., Fan, B., Andersen, D. G., and Kaminsky, M. SILT: A memory-efficient, high-performance key-value store. In Proceedings of the Twenty-Third ACM Symposium on Operating Systems Principles (2011), SOSP '11, pp. 1--13. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Narayanan, D., and Hodson, O. Whole-system persistence. In Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems (2012), ASPLOS XVII, pp. 401--410. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Pelley, S., Chen, P. M., and Wenisch, T. F. Memory persistency. In Proceeding of the 41st Annual International Symposium on Computer Architecuture (2014), ISCA '14, pp. 265--276. Google ScholarGoogle ScholarCross RefCross Ref
  34. Qureshi, M. K., Srinivasan, V., and Rivers, J. A. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (2009), ISCA '09, pp. 24--33. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Ramadan, H. E., Rossbach, C. J., and Witchel, E. Dependence-aware transactional memory for increased concurrency. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (2008), MICRO-41, pp. 246--257. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Raoux, S., Burr, G. W., Breitwisch, M. J., Rettner, C. T., Chen, Y.-C., Shelby, R. M., Salinga, M., Krebs, D., Chen, S.-H., Lung, H.-L., and Lam, C. H. Phase-change random access memory: A scalable technology. IBM J. Res. Dev. 52, 4 (July 2008), 465--479. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Ren, J., Liang, C.-J. M., Wu, Y., and Moscibroda, T. Memory-centric data storage for mobile systems. In Proceedings of the 2015 USENIX Conference on Usenix Annual Technical Conference (2015), USENIX ATC '15, pp. 599--611.Google ScholarGoogle Scholar
  38. Ren, J., Zhao, J., Khan, S., Choi, J., Wu, Y., and Mutlu, O. ThyNVM: Enabling software-transparent crash consistency in persistent memory systems. In Proceedings of the 48th International Symposium on Microarchitecture (2015), MICRO-48, pp. 672--685. http://persper.com/thynvm/.Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. Riegel, T., Fetzer, C., and Felber, P. Time-based transactional memory with scalable time bases. In Proceedings of the Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures (2007), SPAA '07, pp. 221--228. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Rosenblum, M., and Ousterhout, J. K. The design and implementation of a log-structured file system. ACM Trans. Comput. Syst. 10, 1 (Feb. 1992), 26--52. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Rudoff, A. Deprecating the PCOMMIT instruction. https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction, Sept. 2016.Google ScholarGoogle Scholar
  42. Rumble, S. M., Kejriwal, A., and Ousterhout, J. Log-structured memory for DRAM-based storage. In Proceedings of the 12th USENIX Conference on File and Storage Technologies (2014), FAST '14, pp. 1--16.Google ScholarGoogle Scholar
  43. Simo, N., Antoni, W., Markk, M., and Vilho, R. Telecom application transaction processing benchmark. http://tatpbenchmark.sourceforge.net/.Google ScholarGoogle Scholar
  44. Suzuki, K., and Swanson, S. A survey of trends in non-volatile memory technologies: 2000--2014. In 2015 IEEE International Memory Workshop (IMW) (May 2015), pp. 1--4. Google ScholarGoogle ScholarCross RefCross Ref
  45. THE TRANSACTION PROCESSING COUNCIL. TPC-C Benchmark V5. http://www.tpc.org/tpcc/.Google ScholarGoogle Scholar
  46. Tu, S., Zheng, W., Kohler, E., Liskov, B., and Madden, S. Speedy transactions in multicore in-memory databases. In Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles (2013), SOSP '13, pp. 18--32. Google ScholarGoogle ScholarDigital LibraryDigital Library
  47. Volos, H., Tack, A. J., and Swift, M. M. Mnemosyne: Lightweight persistent memory. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems (2011), ASPLOS XVI, pp. 91--104. Google ScholarGoogle ScholarDigital LibraryDigital Library
  48. Wan, H., Lu, Y., Xu, Y., and Shu, J. Empirical study of redo and undo logging in persistent memory. In 2016 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA) (Aug. 2016), pp. 1--6. Google ScholarGoogle ScholarCross RefCross Ref
  49. Wang, C., Chen, W.-Y., Wu, Y., Saha, B., and Adl-Tabatabai, A.-R. Code generation and optimization for transactional memory constructs in an unmanaged language. In Proceedings of the International Symposium on Code Generation and Optimization (2007), CGO '07, pp. 34--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  50. Wang, T., and Johnson, R. Scalable logging through emerging non-volatile memory. Proceedings of the VLDB Endowment 7, 10 (2014), 865--876. Google ScholarGoogle ScholarDigital LibraryDigital Library
  51. Wang, Z., Qian, H., Li, J., and Chen, H. Using restricted transactional memory to build a scalable in-memory database. In Proceedings of the Ninth European Conference on Computer Systems (2014), EuroSys '14, pp. 26:1--26:15. Google ScholarGoogle ScholarDigital LibraryDigital Library
  52. Wei, X., Shi, J., Chen, Y., Chen, R., and Chen, H. Fast in-memory transaction processing using RDMA and H™. In Proceedings of the 25th Symposium on Operating Systems Principles (2015), SOSP '15, pp. 87--104. Google ScholarGoogle ScholarDigital LibraryDigital Library
  53. Wu, M., and Zwaenepoel, W. eNVy: A Non-volatile, Main Memory Storage System. In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems (1994), ASPLOS VI, pp. 86--97. Google ScholarGoogle ScholarDigital LibraryDigital Library
  54. Xu, J., and Swanson, S. NOVA: A log-structured file system for hybrid volatile/non-volatile main memories. In Proceedings of the 14th Usenix Conference on File and Storage Technologies (2016), FAST '16, pp. 323--338.Google ScholarGoogle Scholar
  55. Yang, J., Wei, Q., Chen, C., Wang, C., Yong, K. L., and He, B. NV-Tree: Reducing consistency cost for NVM-based single level systems. In Proceedings of the 13th USENIX Conference on File and Storage Technologies (2015), FAST '15, pp. 167--181.Google ScholarGoogle Scholar
  56. Yoon, J. H., Hunter, H. C., and Tressler, G. A. Flash & DRAM Si scaling challenges, emerging non-volatile memory technology enablement -- implications to enterprise storage and server compute systems. Flash Memory Summit (2013).Google ScholarGoogle Scholar
  57. Zhang, Y., and Swanson, S. A study of application performance with non-volatile main memory. In Proceedings of the 31st Symposium on Mass Storage Systems and Technologies (May 2015), MSST '15, pp. 1--10. Google ScholarGoogle ScholarCross RefCross Ref
  58. Zhao, J., Li, S., Yoon, D. H., Xie, Y., and Jouppi, N. P. Kiln: Closing the performance gap between systems with and without persistence support. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (2013), MICRO-46, pp. 421--432. Google ScholarGoogle ScholarDigital LibraryDigital Library

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        • Published in

          cover image ACM SIGPLAN Notices
          ACM SIGPLAN Notices  Volume 52, Issue 4
          ASPLOS '17
          April 2017
          811 pages
          ISSN:0362-1340
          EISSN:1558-1160
          DOI:10.1145/3093336
          Issue’s Table of Contents
          • cover image ACM Conferences
            ASPLOS '17: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems
            April 2017
            856 pages
            ISBN:9781450344654
            DOI:10.1145/3037697

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          • Published: 4 April 2017

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