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A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits

Published: 11 August 2017 Publication History
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  • Abstract

    Often as the most important arithmetic modules in a processor, adders, multipliers, and dividers determine the performance and energy efficiency of many computing tasks. The demand of higher speed and power efficiency, as well as the feature of error resilience in many applications (e.g., multimedia, recognition, and data analytics), have driven the development of approximate arithmetic design. In this article, a review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers, and dividers. A comprehensive and comparative evaluation of their error and circuit characteristics is performed for understanding the features of various designs. By using approximate multipliers and adders, the circuit for an image processing application consumes as little as 47% of the power and 36% of the power-delay product of an accurate design while achieving similar image processing quality. Improvements in delay, power, and area are obtained for the detection of differences in images by using approximate dividers.

    References

    [1]
    Tinku Acharya and Ajoy K. Ray. 2005. Image Processing: Principles and Applications. John Wiley 8 Sons.
    [2]
    Shaahin Angizi, Zhezhi He, Ronald F. DeMara, and Deliang Fan. 2017. Composite spintronic accuracy-configurable adder for low power digital signal processing. In Proceedings of the 2017 18th International Symposium on Quality Electronic Design (ISQED’17). IEEE, Los Alamitos, CA.
    [3]
    Dursun Baran, Mustafa Aktan, and Vojin G. Oklobdzija. 2010. Energy efficient implementation of parallel CMOS multipliers with improved compressors. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. ACM, New York, NY, 147--152.
    [4]
    Kartikeya Bhardwaj, Pravin S. Mane, and Jorg Henkel. 2014. Power- and area-efficient approximate Wallace tree multiplier for error-resilient systems. In Proceedings of the 2014 15th International Symposium on Quality Electronic Design (ISQED’14). 263--269.
    [5]
    Hao Cai, You Wang, Lirida A. B. Naviner, Zhaohao Wang, and Weisheng Zhao. 2016. Approximate computing in MOS/spintronic non-volatile full-adder. In Proceedings of the 2016 International Symposium on Nanoscale Architectures (NANOARCH’16). IEEE, Los Alamitos, CA, 203--208.
    [6]
    Vincent Camus, Jeremy Schlachter, and Christian Enz. 2016. A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision. In Proceedings of the 53rd Annual Design Automation Conference. ACM, New York, NY, 127.
    [7]
    Linbin Chen, Jie Han, Weiqiang Liu, and Fabrizio Lombardi. 2015. Design of approximate unsigned integer non-restoring divider for inexact computing. In Proceedings of the 25th edition of the Great Lakes Symposium on VLSI (GLSVLSI’15). ACM, New York, NY, 51--56.
    [8]
    Linbin Chen, Jie Han, Weiqiang Liu, and Fabrizio Lombardi. 2016. On the design of approximate restoring dividers for error-tolerant applications. IEEE Transactions on Computers 65, 8, 2522--2533.
    [9]
    Yuan-Ho Chen and Tsin-Yuan Chang. 2012. A high-accuracy adaptive conditional-probability estimator for fixed-width Booth multipliers. IEEE Transactions on Circuits and Systems I: Regular Papers 59, 3, 594--603.
    [10]
    Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, and Srimat T. Chakradhar. 2010. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency. In Proceedings of the 2010 47th ACM/IEEE Design Automation Conference (DAC’10). ACM, New York, NY, 555--560.
    [11]
    Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, and Keshab K. Parhi. 2004. Design of low-error fixed-width modified booth multiplier. IEEE Transactions on VLSI Systems 12, 5, 522--531.
    [12]
    S. R. Datla, M. A Thornton, and D. W. Matula. 2009. A low power high performance radix-4 approximate squaring circuit. In Proceedings of the 2009 20th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’09). 91--97.
    [13]
    K. Du, P. Varman, and K. Mohanram. 2012. High performance reliable variable latency carry select addition. In Proceedings of the 2012 Design, Automation, and Test in Europe Conference and Exhibition (DATE’12). 1257--1262.
    [14]
    Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, and Doug Burger. 2012. Architecture support for disciplined approximate programming. ACM SIGPLAN Notices 47, 301--312.
    [15]
    Farzad Farshchi, Muhammad Saeed Abrishami, and Sied Mehdi Fakhraie. 2013. New approximate multiplier for low power digital signal processing. In Proceedings of the 2013 17th CSI International Symposium on Computer Architecture and Digital Systems (CADS’13). IEEE, Los Alamitos, CA, 25--30.
    [16]
    Michael J. Flynn. 1970. On division by functional iteration. IEEE Transactions on Computers 100, 8, 702--706.
    [17]
    V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy. 2013. Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, 1, 124--137.
    [18]
    Jie Han. 2016. Introduction to approximate computing. In Proceedings of the 2016 34th IEEE VLSI Test Symposium (VTS’16). IEEE, Los Alamitos, CA, 1.
    [19]
    Jie Han and Michael Orshansky. 2013. Approximate computing: An emerging paradigm for energy-efficient design. In Proceedings of the 2013 18th IEEE European Test Symposium (ETS’13). IEEE, Los Alamitos, CA, 1--6.
    [20]
    S. Hashemi, R. Bahar, and S. Reda. 2015. Drum: A dynamic range unbiased multiplier for approximate applications. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. IEEE, Los Alamitos, CA, 418--425.
    [21]
    S. Hashemi, R. Bahar, and S. Reda. 2016. A low-power dynamic divider for approximate applications. In Proceedings of the 53rd Annual Design Automation Conference. ACM, New York, NY, 105.
    [22]
    Junjun Hu and Weikang Qian. 2015. A new approximate adder with low relative error and correct sign calculation. In Proceedings of the 2015 Design, Automation, and Test in Europe Conference and Exhibition (DATE’15). 1449--1454.
    [23]
    Jiawei Huang, John Lach, and Gabriel Robins. 2012. A methodology for energy-quality tradeoff using imprecise hardware. In Proceedings of the 49th ACM Annual Design Automation Conference. 504--509.
    [24]
    Honglan Jiang, Jie Han, and Fabrizio Lombardi. 2015. A comparative review and evaluation of approximate adders. In Proceedings of 2015 ACM Great Lakes Symposium on VLSI. 343--348.
    [25]
    Honglan Jiang, Jie Han, and Fabrizio Lombardi. 2016a. Approximate radix-8 booth multiplier for low-power and high-performance operation. IEEE Transactions on Computers 65, 8, 2638--2644.
    [26]
    Honglan Jiang, Jie Han, and Fabrizio Lombardi. 2016b. A comparative evaluation of approximate multipliers. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures.
    [27]
    Andrew B. Kahng and Seokhyeong Kang. 2012. Accuracy-configurable adder for approximate arithmetic designs. In Proceedings of the 49th ACM Annual Design Automation Conference. 820--825.
    [28]
    D. Kelly, B. Phillips, and S. Al-Sarawi. 2009. Approximate signed binary integer multipliers for arithmetic data value speculation. In Proceedings of the 2009 Conference on Design and Architectures for Signal and Image Processing.
    [29]
    Yongtae Kim, Yong Zhang, and Peng Li. 2013. An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems. In Proceedings of the 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’13). 130--137.
    [30]
    Parag Kulkarni, Puneet Gupta, and Milos Ercegovac. 2011. Trading accuracy for power with an underdesigned multiplier architecture. In Proceedings of the 2011 International Conference on VLSI Design. 346--351.
    [31]
    Khaing Yin Kyaw, Wang Ling Goh, and Kiat Seng Yeo. 2010. Low-power high-speed multiplier for error-tolerant application. In Proceedings of the 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC’10). 1--4.
    [32]
    Mark S. K. Lau, Keck-Voon Ling, and Yun-Chung Chu. 2009. Energy-aware probabilistic multiplier: Design and analysis. In Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’09). 281--290.
    [33]
    Li Li and Hai Zhou. 2014. On error modeling and analysis of approximate adders. In Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’14). 511--518.
    [34]
    J. Liang, J. Han, and F. Lombardi. 2013. New metrics for the reliability of approximate and probabilistic adders. IEEE Transactions on Computers 62, 9, 1760--1771.
    [35]
    Chia-Hao Lin and Ing-Chao Lin. 2013. High accuracy approximate multiplier with error correction. In Proceedings of the 2013 IEEE 31st International Conference on Computer Design (ICCD’13). IEEE, Los Alamitos, CA, 33--38.
    [36]
    Ing-Chao Lin, Yi-Ming Yang, and Cheng-Chian Lin. 2015. High-performance low-power carry speculative addition with variable latency. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, 9, 1591--1603.
    [37]
    Cong Liu. 2014. Design and Analysis of Approximate Adders and Multipliers. Master’s Thesis. University of Alberta, Canada.
    [38]
    Cong Liu, Jie Han, and Fabrizio Lombardi. 2014. A low-power, high-performance approximate multiplier with configurable partial error recovery. In Proceedings of the 2014 Design, Automation, and Test in Europe Conference and Exhibition (DATE’14).
    [39]
    Cong Liu, Jie Han, and Fabrizio Lombardi. 2015. An analytical framework for evaluating the error characteristics of approximate adders. IEEE Transactions on Computers 64, 5, 1268--1281.
    [40]
    Cong Liu, Honglan Jiang, Fabrizio Lombardi, and Jie Han. 2017a. High-performance approximate unsigned multipliers with configurable error recovery. IEEE Transactions on Circuits and Systems I. Under revision.
    [41]
    Wei Liu and Alberto Nannarelli. 2012. Power efficient division and square root unit. IEEE Transactions on Computers 61, 8, 1059--1070.
    [42]
    Weiqiang Liu, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, and Fabrizio Lombardi. 2017b. Design of approximate radix-4 booth multipliers for error-tolerant computing. IEEE Transactions on Computers PP, 99, 1.
    [43]
    Joshua Yung Lih Low and Ching Chuen Jong. 2013. Non-iterative high speed division computation based on Mitchell logarithmic method. In Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS’13). 2219--2222.
    [44]
    Shih-Lien Lu. 2004. Speeding up processing with approximation circuits. Computer 37, 3, 67--73.
    [45]
    Jieming Ma, Ka Lok Man, Nan Zhang, Sheng-Uei Guan, and Taikyeong Ted Jeong. 2013. High-speed area-efficient and power-aware multiplier design using approximate compressors along with bottom-up tree topology. In Proceedings of SPIE 8784: The 5th International Conference on Machine Vision (ICMV’12): Algorithms, Pattern Recognition, and Basic Technologies. 87841Z.
    [46]
    H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas. 2010. Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Transactions on Circuits and Systems 57, 4, 850--862.
    [47]
    Sana Mazahir, Osman Hasan, Rehan Hafiz, Muhammad Shafique, and Jörg Henkel. 2017. Probabilistic error modeling for approximate adders. IEEE Transactions on Computers 66, 3, 515--530.
    [48]
    Jin Miao, Ku He, Andreas Gerstlauer, and Michael Orshansky. 2012. Modeling and synthesis of quality-energy optimal approximate adders. In Proceedings of the 2012 ACM International Conference on Computer-Aided Design. 728--735.
    [49]
    Joshua San Miguel, Jorge Albericio, Andreas Moshovos, and Natalie Enright Jerger. 2015. Doppelgänger: A cache for approximate computing. In Proceedings of the 2015 48th International Symposium on Microarchitecture. ACM, New York, NY, 50--61.
    [50]
    John N. Mitchell Jr. 1962. Computer multiplication and division using binary logarithms. IRE Transactions on Electronic Computers 4, 512--517.
    [51]
    D. Mohapatra, V. K. Chippa, A. Raghunathan, and K. Roy. 2011. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of the 2011 Design, Automation, and Test in Europe Conference and Exhibition (DATE’11). 1--6.
    [52]
    Amir Momeni, Jie Han, Paolo Montuschi, and Fabrizio Lombardi. 2015. Design and analysis of approximate compressors for multiplication. IEEE Transactions on Computers 64, 4, 984--994.
    [53]
    Vojtech Mrazek, Syed Shakib Sarwar, Lukas Sekanina, Zdenek Vasicek, and Kaushik Roy. 2016. Design of power-efficient approximate multipliers for approximate artificial neural networks. In Proceedings of the 2016 International Conference on Computer Aided Design (ICCAD’16). 7.
    [54]
    Srinivasan Narayanamoorthy, Hadi Asghari Moghaddam, Zhenhong Liu, Taejoon Park, and Nam Sung Kim. 2015. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, 6, 1180--1184.
    [55]
    Vojin G. Oklobdzija, David Villeger, and Simon S. Liu. 1996. A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Transactions on Computers 45, 3, 294--306.
    [56]
    Behrooz Parhami. 2000. Computer Arithmetic. Oxford University Press, Oxford, England.
    [57]
    Adrian Sampson, Werner Dietl, Emily Fortuna, Danushen Gnanapragasam, Luis Ceze, and Dan Grossman. 2011. EnerJ: Approximate data types for safe and general low-power computation. ACM SIGPLAN Notices 46, 6, 164--174.
    [58]
    Doochul Shin. 2010. Approximate logic synthesis for error tolerant applications. In Proceedings of the 2010 Design, Automation, and Test in Europe Conference and Exhibition (DATE’10). IEEE, Los Alamitos, CA, 957--960.
    [59]
    Min-An Song, Lan-Da Van, and Sy-Yen Kuo. 2007. Adaptive low-error fixed-width Booth multipliers. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 90, 6, 1180--1187.
    [60]
    Zdenek Vasicek and Lukas Sekanina. 2015. Evolutionary approach to approximate digital circuits design. IEEE Transactions on Evolutionary Computation 19, 3, 432--444.
    [61]
    Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan. 2010. MACACO: Modeling and analysis of circuits for approximate computing. In Proceedings of the 2010 International Conference on Computer-Aided Design (ICCAD’11). 667--673.
    [62]
    Ajay K. Verma, Philip Brisk, and Paolo Ienne. 2008. Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the 2008 Conference on Design, Automation, and Test in Europe (DATE’08). 1250--1255.
    [63]
    Jiun-Ping Wang, Shiann-Rong Kuang, and Shish-Chang Liang. 2011. High-accuracy fixed-width modified Booth multipliers for lossy applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 1, 52--60.
    [64]
    Lei Wu and Ching Chuen Jong. 2015. A curve fitting approach for non-iterative divider design with accuracy and performance trade-off. In Proceedings of the 2015 13th IEEE International New Circuits and Systems Conference (NEWCAS’15). 1--4.
    [65]
    Xinghua Yang, Yue Xing, Fei Qiao, Qi Wei, and Huazhong Yang. 2016. Approximate adder with hybrid prediction and error compensation technique. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’16)). IEEE, Los Alamitos, CA, 373--378.
    [66]
    Zhixi Yang, Ajaypat Jain, Jinghang Liang, Jie Han, and Fabrizio Lombardi. 2013. Approximate XOR/XNOR-based adders for inexact computing. In Proceedings of the 2013 13th IEEE Conference on Nanotechnology (IEEE-NANO’13). 690--693.
    [67]
    Rong Ye, Ting Wang, Feng Yuan, Rakesh Kumar, and Qiang Xu. 2013. On reconfiguration-oriented approximate adder design and its application. In Proceedings of the 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’13). 48--54.
    [68]
    Reza Zendegani, Mehdi Kamal, Milad Bahadori, Ali Afzali-Kusha, and Massoud Pedram. 2017. RoBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, 2, 393--401.
    [69]
    Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, and Massoud Pedram. 2016. SEERAD: A high speed yet energy-efficient rounding-based approximate divider. In Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition (DATE’16). IEEE, Los Alamitos, CA, 1481--1484.
    [70]
    Ning Zhu, Wang Ling Goh, and Kiat Seng Yeo. 2009. An enhanced low-power high-speed adder for error-tolerant application. In Proceedings of the 2009 12th International Symposium on Integrated Circuits (ISIC’09). 69--72.

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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 13, Issue 4
    October 2017
    267 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/3098274
    • Editor:
    • Yuan Xie
    Issue’s Table of Contents
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    Publication History

    Published: 11 August 2017
    Accepted: 01 April 2017
    Revised: 01 January 2017
    Received: 01 September 2016
    Published in JETC Volume 13, Issue 4

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    Author Tags

    1. Approximate computing
    2. accuracy
    3. adder
    4. approximate circuit
    5. divider
    6. hardware
    7. image processing
    8. multiplier

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    • University of Alberta and the Natural Sciences and Engineering Research Council (NSERC) of Canada

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