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Exploiting Approximate MLC-PCM in Low-Power Embedded Systems

Published:06 December 2017Publication History
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Abstract

Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.

References

  1. Aaron Carroll and Gernot Heiser. 2010. An analysis of power consumption in a smartphone. In Proceedings of the USENIX Annual Technical Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Da-Wei Chang, Chao Lin, Yu-Shiang Chien, Chin-Lun Lin, Alvin W-Y Su, and Chung-Ping Young. 2014. CASA: Contention-aware scratchpad memory allocation for online hybrid on-chip memory management. IEEE Trans. Comput.-Aided Design of Integr. Circuits and Syst. 33, 12 (2014), 1806--1817.Google ScholarGoogle ScholarCross RefCross Ref
  3. Gabriel Rodríguez, Juan Tourino, and Mahmut T. Kandemir. 2015. Volatile STT-RAM scratchpad design and data allocation for low energy. ACM Trans. on Archit. Code Optimization (TACO) 11, 4 (2015), 38:1--38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, and Doug Burger. 2010. Phase-change technology and the future of main memory. IEEE Micro 30, 1 (2010), 131--141. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, and Bruce R. Childers. 2012. Improving write operations in MLC phase change memory. In Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture (HPCA’12). Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Adrian Sampson, Jacob Nelson, Karin Strauss, and Luis Ceze. 2013. Approximate storage in solid-state memories. In 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 25--36. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Majid Shoushtari, Abbas BanaiyanMofrad, and Nikil Dutt. 2015. Exploiting partially-forgetful memories for approximate computing. IEEE Embedded Systems Letters 7, 1 (2015), 19--22.Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and Viji Srinivasan. 2012. Efficient scrub mechanisms for error-prone emerging memories. In Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture (HPCA’12). Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Geoffrey W. Burr, Matthew J. Breitwisch, Michele Franceschini, Davide Garetto, Kailash Gopalakrishnan, Bryan Jackson, Blent Kurdi, Chung Lam, Luis A. Lastras, Alvaro Padilla, Bipin Rajendran, Simone Raoux, and Rohit S. Shenoy. 2010. Phase change memory technology. J. Vacuum Sci. Technol. B 28 (2010), 223--262.Google ScholarGoogle ScholarCross RefCross Ref
  10. Jun-Tin Lin, Yi-Bo Liao, Meng-Hsueh Chiang, I Chiu, Chia-Long Lin, Wei-Chou Hsu, Pei-Chia Chiang, Shyh-Shyuan Sheu, Yen-Ya Hsu, Wen-Hsing Liu, et al. 2009. Design optimization in write speed of multi-level cell application for phase change memory. In Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC’09).Google ScholarGoogle Scholar
  11. Jun-Tin Lin, Yi-Bo Liao, Meng-Hsueh Chiang, and Wei-Chou Hsu. 2009. Operation of multi-level phase change memory using various programming techniques. In Proceedings of the IEEE International Conference on IC Design and Technology.Google ScholarGoogle ScholarCross RefCross Ref
  12. Qingan Li, Lei Jiang, Youtao Zhang, Yanxiang He, and Chun Jason Xue. 2013. Compiler directed write-mode selection for high performance low power volatile PCM. In ACM SIGPLAN Notices. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Jing Li, Binquan Luan, and Chung Lam. 2012. Resistance drift in phase change memory. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS’12).Google ScholarGoogle ScholarCross RefCross Ref
  14. Wangyuan Zhang and Tao Li. 2011. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In Proceedings of the IEEE/IFIP International Conference on Dependable Systems Networks (DSN’11). Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Sungkap Yeo, Nak Hee Seong, and Hsien-Hsin S. Lee. 2012. Can multi-level cell PCM be reliable and usable? Analyzing the impact of resistance drift. In Proceedings of the Workshop on Duplicating, Deconstructing and Debunking.Google ScholarGoogle Scholar
  16. Wei Xu and Tong Zhang. 2011. A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift. IEEE Trans. on Very Large Scale Integr. (VLSI) Syst. 19, 8 (2011), 1357--1367. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Wei Xu and Tong Zhang. 2010. Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory. In Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED’10).Google ScholarGoogle Scholar
  18. Chen Pan, Mimi Xie, Jingtong Hu, Yiran Chen, and Chengmo Yang. 2014. 3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems. In Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS’14). Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Keni Qiu, Qingan Li, and Chun Jason Xue. 2014. Write mode aware loop tiling for high performance low power volatile PCM. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14). Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Majid Jalili and Hamid Sarbazi-Azad. 2014. A compression-based morphable PCM architecture for improving resistance drift tolerance. In Proceedings of the 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP’14).Google ScholarGoogle ScholarCross RefCross Ref
  21. Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Comput. Archit. News 37, 3 (2009), 24--33. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, Kwang-Jin Lee, Chang-Soo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, et al. 2007. A 0.1-m 1.8-v 256-mb phase-change random access memory (pram) with 66-mhz synchronous burst-read operation. IEEE J. Solid-State Circuits 42, 1 (2007), 210--218.Google ScholarGoogle ScholarCross RefCross Ref
  23. Daniele Ielmini, Andrea L. Lacaita, and Davide Mantegazza. 2007. Recovery and drift dynamics of resistance and threshold voltages in phase-change memories. IEEE Trans. on Electron Devices 54, 2 (2007), 308--315.Google ScholarGoogle ScholarCross RefCross Ref
  24. Chang-Wook Jeong, Dae-Hwan Kang, Hyeong-Jun Kim, KO Seung-Pil, and Dong-won Lim. 2010. Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices. (2010). U.S. Patent No. 7,701,749. Mar 28, 2008, April 20, 2010.Google ScholarGoogle Scholar
  25. M. Boniardi, D. Ielmini, S. Lavizzari, A.L. Lacaita, A. Redaelli, and A. Pirovano. 2009. Statistical and scaling behavior of structural relaxation effects in phase-change memory (PCM) devices. In Proceedigns of the IEEE International Reliability Physics Symposium.Google ScholarGoogle Scholar
  26. Daniele Ielmini, Deepak Sharma, Simone Lavizzari, and Andrea L. Lacaita. 2009. Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells. Part I: Experimental study. IEEE Trans. on Electron Devices 56, 5 (2009), 1070--1077.Google ScholarGoogle ScholarCross RefCross Ref
  27. Song Liu, Karthik Pattabiraman, Thomas Moscibroda, and Benjamin G. Zorn. 2009. Flicker: Saving Refresh-Power in Mobile Devices Through Critical Data Partitioning. Technical report. Microsoft Research.Google ScholarGoogle Scholar
  28. Michael Carbin and Martin C. Rinard. 2010. Automatically identifying critical input regions and code in applications. In Proceedings of the 19th International Symposium on Software Testing and Analysis. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, and Anand Raghunathan. 2013. Analysis and characterization of inherent application resilience for approximate computing. In Proceedings of the 50th Annual Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Weixun Wang and Prabhat Mishra. 2010. Leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in real-time systems. In Proceedings of the 23rd International Conference on VLSI Design (VLSID’10). Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Ravindra Jejurikar, Cristiano Pereira, and Rajesh Gupta. 2004. Leakage aware dynamic voltage scaling for real-time embedded systems. In Proceedings of the 41st Annual Design Automation Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. IBM. 2007. ILOG Cplex. 11.0 Users Manual. IBM. Available at http://www.ilog.com/products/cplex/.Google ScholarGoogle Scholar
  33. Yuanrui Zhang and Mahmut Kandemir. 2009. A hardware-software codesign strategy for loop intensive applications. In Proceedings of the 7th IEEE Symposium on Application Specific Processors (SASP’09).Google ScholarGoogle ScholarCross RefCross Ref
  34. Doug Burger and Todd M. Austin. 1997. The simplescalar tool set, version 2.0. ACM SIGARCH Computer Architecture News 25, 3 (1997), 13--25. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Xiangyu Dong, Norman P. Jouppi, and Yuan Xie. 2009. PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM. In Proceedings of the International Conference on Computer-Aided Design. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. ATMEL. 2012. 32-bit AVR Microcontroller. Retrieved from http://www.atmel.com/products/microcontrollers/avr/.Google ScholarGoogle Scholar
  37. Matthew R. Guthaus, Jeffrey S. Ringenberg, Dan Ernst, Todd M. Austin, Trevor Mudge, and Richard B. Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE International Workshop on Workload Characterization. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. Chunho Lee, Miodrag Potkonjak, and William H Mangione-Smith. 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. Khalid Sayood et al. 2002. Statistical evaluation of image quality measures. J. Electron. Imaging 11, 2 (2002), 206--223.Google ScholarGoogle ScholarCross RefCross Ref
  40. Pushpajit A. Khaire and Nileshsingh V. Thakur. 2012. A fuzzy set approach for edge detection. Int. J. Image Process. (IJIP) 6, 6 (2012), 403--412.Google ScholarGoogle Scholar

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