Abstract
Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.
- Aaron Carroll and Gernot Heiser. 2010. An analysis of power consumption in a smartphone. In Proceedings of the USENIX Annual Technical Conference. Google Scholar
Digital Library
- Da-Wei Chang, Chao Lin, Yu-Shiang Chien, Chin-Lun Lin, Alvin W-Y Su, and Chung-Ping Young. 2014. CASA: Contention-aware scratchpad memory allocation for online hybrid on-chip memory management. IEEE Trans. Comput.-Aided Design of Integr. Circuits and Syst. 33, 12 (2014), 1806--1817.Google Scholar
Cross Ref
- Gabriel Rodríguez, Juan Tourino, and Mahmut T. Kandemir. 2015. Volatile STT-RAM scratchpad design and data allocation for low energy. ACM Trans. on Archit. Code Optimization (TACO) 11, 4 (2015), 38:1--38. Google Scholar
Digital Library
- Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, and Doug Burger. 2010. Phase-change technology and the future of main memory. IEEE Micro 30, 1 (2010), 131--141. Google Scholar
Digital Library
- Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, and Bruce R. Childers. 2012. Improving write operations in MLC phase change memory. In Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture (HPCA’12). Google Scholar
Digital Library
- Adrian Sampson, Jacob Nelson, Karin Strauss, and Luis Ceze. 2013. Approximate storage in solid-state memories. In 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 25--36. Google Scholar
Digital Library
- Majid Shoushtari, Abbas BanaiyanMofrad, and Nikil Dutt. 2015. Exploiting partially-forgetful memories for approximate computing. IEEE Embedded Systems Letters 7, 1 (2015), 19--22.Google Scholar
Digital Library
- M. Awasthi, M. Shevgoor, K. Sudan, B. Rajendran, R. Balasubramonian, and Viji Srinivasan. 2012. Efficient scrub mechanisms for error-prone emerging memories. In Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture (HPCA’12). Google Scholar
Digital Library
- Geoffrey W. Burr, Matthew J. Breitwisch, Michele Franceschini, Davide Garetto, Kailash Gopalakrishnan, Bryan Jackson, Blent Kurdi, Chung Lam, Luis A. Lastras, Alvaro Padilla, Bipin Rajendran, Simone Raoux, and Rohit S. Shenoy. 2010. Phase change memory technology. J. Vacuum Sci. Technol. B 28 (2010), 223--262.Google Scholar
Cross Ref
- Jun-Tin Lin, Yi-Bo Liao, Meng-Hsueh Chiang, I Chiu, Chia-Long Lin, Wei-Chou Hsu, Pei-Chia Chiang, Shyh-Shyuan Sheu, Yen-Ya Hsu, Wen-Hsing Liu, et al. 2009. Design optimization in write speed of multi-level cell application for phase change memory. In Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC’09).Google Scholar
- Jun-Tin Lin, Yi-Bo Liao, Meng-Hsueh Chiang, and Wei-Chou Hsu. 2009. Operation of multi-level phase change memory using various programming techniques. In Proceedings of the IEEE International Conference on IC Design and Technology.Google Scholar
Cross Ref
- Qingan Li, Lei Jiang, Youtao Zhang, Yanxiang He, and Chun Jason Xue. 2013. Compiler directed write-mode selection for high performance low power volatile PCM. In ACM SIGPLAN Notices. Google Scholar
Digital Library
- Jing Li, Binquan Luan, and Chung Lam. 2012. Resistance drift in phase change memory. In Proceedings of the IEEE International Reliability Physics Symposium (IRPS’12).Google Scholar
Cross Ref
- Wangyuan Zhang and Tao Li. 2011. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In Proceedings of the IEEE/IFIP International Conference on Dependable Systems Networks (DSN’11). Google Scholar
Digital Library
- Sungkap Yeo, Nak Hee Seong, and Hsien-Hsin S. Lee. 2012. Can multi-level cell PCM be reliable and usable? Analyzing the impact of resistance drift. In Proceedings of the Workshop on Duplicating, Deconstructing and Debunking.Google Scholar
- Wei Xu and Tong Zhang. 2011. A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift. IEEE Trans. on Very Large Scale Integr. (VLSI) Syst. 19, 8 (2011), 1357--1367. Google Scholar
Digital Library
- Wei Xu and Tong Zhang. 2010. Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory. In Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED’10).Google Scholar
- Chen Pan, Mimi Xie, Jingtong Hu, Yiran Chen, and Chengmo Yang. 2014. 3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems. In Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS’14). Google Scholar
Digital Library
- Keni Qiu, Qingan Li, and Chun Jason Xue. 2014. Write mode aware loop tiling for high performance low power volatile PCM. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14). Google Scholar
Digital Library
- Majid Jalili and Hamid Sarbazi-Azad. 2014. A compression-based morphable PCM architecture for improving resistance drift tolerance. In Proceedings of the 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP’14).Google Scholar
Cross Ref
- Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Comput. Archit. News 37, 3 (2009), 24--33. Google Scholar
Digital Library
- Sangbeom Kang, Woo Yeong Cho, Beak-Hyung Cho, Kwang-Jin Lee, Chang-Soo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, et al. 2007. A 0.1-m 1.8-v 256-mb phase-change random access memory (pram) with 66-mhz synchronous burst-read operation. IEEE J. Solid-State Circuits 42, 1 (2007), 210--218.Google Scholar
Cross Ref
- Daniele Ielmini, Andrea L. Lacaita, and Davide Mantegazza. 2007. Recovery and drift dynamics of resistance and threshold voltages in phase-change memories. IEEE Trans. on Electron Devices 54, 2 (2007), 308--315.Google Scholar
Cross Ref
- Chang-Wook Jeong, Dae-Hwan Kang, Hyeong-Jun Kim, KO Seung-Pil, and Dong-won Lim. 2010. Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices. (2010). U.S. Patent No. 7,701,749. Mar 28, 2008, April 20, 2010.Google Scholar
- M. Boniardi, D. Ielmini, S. Lavizzari, A.L. Lacaita, A. Redaelli, and A. Pirovano. 2009. Statistical and scaling behavior of structural relaxation effects in phase-change memory (PCM) devices. In Proceedigns of the IEEE International Reliability Physics Symposium.Google Scholar
- Daniele Ielmini, Deepak Sharma, Simone Lavizzari, and Andrea L. Lacaita. 2009. Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cells. Part I: Experimental study. IEEE Trans. on Electron Devices 56, 5 (2009), 1070--1077.Google Scholar
Cross Ref
- Song Liu, Karthik Pattabiraman, Thomas Moscibroda, and Benjamin G. Zorn. 2009. Flicker: Saving Refresh-Power in Mobile Devices Through Critical Data Partitioning. Technical report. Microsoft Research.Google Scholar
- Michael Carbin and Martin C. Rinard. 2010. Automatically identifying critical input regions and code in applications. In Proceedings of the 19th International Symposium on Software Testing and Analysis. Google Scholar
Digital Library
- Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, and Anand Raghunathan. 2013. Analysis and characterization of inherent application resilience for approximate computing. In Proceedings of the 50th Annual Design Automation Conference. Google Scholar
Digital Library
- Weixun Wang and Prabhat Mishra. 2010. Leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in real-time systems. In Proceedings of the 23rd International Conference on VLSI Design (VLSID’10). Google Scholar
Digital Library
- Ravindra Jejurikar, Cristiano Pereira, and Rajesh Gupta. 2004. Leakage aware dynamic voltage scaling for real-time embedded systems. In Proceedings of the 41st Annual Design Automation Conference. Google Scholar
Digital Library
- IBM. 2007. ILOG Cplex. 11.0 Users Manual. IBM. Available at http://www.ilog.com/products/cplex/.Google Scholar
- Yuanrui Zhang and Mahmut Kandemir. 2009. A hardware-software codesign strategy for loop intensive applications. In Proceedings of the 7th IEEE Symposium on Application Specific Processors (SASP’09).Google Scholar
Cross Ref
- Doug Burger and Todd M. Austin. 1997. The simplescalar tool set, version 2.0. ACM SIGARCH Computer Architecture News 25, 3 (1997), 13--25. Google Scholar
Digital Library
- Xiangyu Dong, Norman P. Jouppi, and Yuan Xie. 2009. PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM. In Proceedings of the International Conference on Computer-Aided Design. Google Scholar
Digital Library
- ATMEL. 2012. 32-bit AVR Microcontroller. Retrieved from http://www.atmel.com/products/microcontrollers/avr/.Google Scholar
- Matthew R. Guthaus, Jeffrey S. Ringenberg, Dan Ernst, Todd M. Austin, Trevor Mudge, and Richard B. Brown. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE International Workshop on Workload Characterization. Google Scholar
Digital Library
- Chunho Lee, Miodrag Potkonjak, and William H Mangione-Smith. 1997. MediaBench: A tool for evaluating and synthesizing multimedia and communicatons systems. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture. Google Scholar
Digital Library
- Khalid Sayood et al. 2002. Statistical evaluation of image quality measures. J. Electron. Imaging 11, 2 (2002), 206--223.Google Scholar
Cross Ref
- Pushpajit A. Khaire and Nileshsingh V. Thakur. 2012. A fuzzy set approach for edge detection. Int. J. Image Process. (IJIP) 6, 6 (2012), 403--412.Google Scholar
Index Terms
Exploiting Approximate MLC-PCM in Low-Power Embedded Systems
Recommendations
Write-aware memory management for hybrid SLC-MLC PCM memory systems
In recent years, phase-change memory (PCM) has generated a great deal of interest because of its byte addressability and non-volatility properties. It is regarded as a good alternative storage medium that can reduce the performance gap between the main ...
Power-Utility-Driven Write Management for MLC PCM
Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing SystemsPhase change memory (PCM) is a promising alternative to Dynamic Random Access Memory (DRAM) as main memory due to its merits of high density and low leakage power. Multi-level Cell (MLC) PCM is more attractive than Single-level Cell (SLC) PCM, because ...
Enabling Hybrid PCM Memory System with Inherent Memory Management
RACS '16: Proceedings of the International Conference on Research in Adaptive and Convergent SystemsReplacing the traditional volatile main memory, e.g., DRAM, with a non-volatile phase change memory (PCM) has become a possible solution to reduce the energy consumption of computing systems. To further reduce the bit cost of PCM, the development trend ...






Comments