Abstract
By scaling down to smaller cell size, NAND flash has significantly increased the storage capacity in order to lower the unit cost down. However, the reliability is sacrificed due to much higher raw bit error rates. As a result, conventional error correction codes (ECCs), such as BCH codes, are not sufficient. Low-density parity check (LDPC) codes with stronger error correction capability are adopted in NAND flash to guarantee data reliability. However, read performance using LDPC is poor because of its decoding complexity. It has been found that flash cells with fewer electrons are more prone to program interference errors. As a result, program interference errors show the characteristic of value dependence. This characteristic can be exploited and translated into extra information facilitating the decoding convergence. Motivated by this observation, we propose PEAL: a flash <underline>p</underline>rogram interference <underline>e</underline>rror <underline>a</underline>ware <underline>L</underline>DPC scheme to enhance the decoding performance. PEAL integrates the obtained extra information from the value dependence into the soft-to-hard decision process in LDPC decoding to decrease decoding iterations and improve the decoding convergence speed. Simulation results show that decoding iterations are reduced by up to 69.37% and the decoding convergence speed is improved by up to 2.5×, compared with the normalized min-sum (NMS) algorithm with 2KB information lengths at an approximate raw bit error rate of 11.5 × 10−3.
- Y. Cai, E. Haratsch, O. Mutlu, and K. Mai. 2012. Error patterns in MLC NAND flash memory: measurement, characterization, and analysis. In Proceedings of the IEEE/ACM Design, Automation 8 Test in Europe Conference (DATE’12). IEEE/ACM, Dresden, Germany, 521--526. Google Scholar
Digital Library
- Y. Cai, O. Mutlu, E. Haratsch, and K. Ma. 2013. Program interference in MLC NAND flash memory: characterization modeling and mitigation. In Proceddigns of the 31st IEEE International Conference on Computer Design (ICCD’13). IEEE, Asheville, NC, USA, 123--130.Google Scholar
- K. Zhao, W. Zhao, H. Sun, T. Zhang, X. Zhang, and N. Zheng. 2013. LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives. In Proceedings of the 11st USENIX Conference on File and Storage Technologies (FAST’13). USENIX. Santa Clara, CA, USA, 244--256. Google Scholar
Digital Library
- G. Dong, N. Xie, and T. Zhang. 2011. On the use of soft-decision error-correction codes in NAND flash memory. IEEE Trans. Circuits Syst.I-Regular Paper. 58, 2 (Feb. 2011), 429--439.Google Scholar
Cross Ref
- W. Zhao, H. Sun, M. Lv, G. Dong, N. Zheng, and T. Zhang. 2014. Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory. In Proceedigns of the 30th IEEE Symposium on Mass Storage Systems and Technologies (MSST’14). IEEE, Santa Clara, CA, USA, 1--6.Google Scholar
- Y. Pan, G. Dong, Q. Wu, and T. Zhang. 2012. Quasi-Nonvolatile SSD: trading flash memory nonvolatility to improve storage system performance for enterprise applications. In Proceedings of the 18th IEEE International Symposium on High-Performance Comp Architecture (HPCA’12). IEEE, New Orleans, LA, USA, 1--10. Google Scholar
Digital Library
- Y. Cai, E. Haratsch, O. Mutlu, and K. Mai. 2013. Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. In Proceedings of the IEEE/ACM Design, Automation 8 Test in Europe Conference (DATE’13). IEEE/ACM, Grenoble, Franch, 1285--1290. Google Scholar
Digital Library
- Y. Cai, G. Yalcin, O. Mutlu, E. Haratsch, O. Unsal, A. Cristal, and K. Mai. 2014. Neighbor-cell assisted error correction for MLC NAND flash memories. In Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS’14). ACM, Austin, Texas, USA, 491--504. Google Scholar
Digital Library
- C. Cao and I. Fair. 2016. Mitigation of inter-cell interference in flash memory with capacity-approaching variable-length constrained sequence codes. IEEE Journal on Selected Areas in Communications. 34, 9 (Sep. 2016), 2366--2377. Google Scholar
Digital Library
- V. Taranalli, H. Uchikawa, and P. Siegel. 2015. Error analysis and inter-cell interference mitigation in multi-level cell flash memories. In Proceedings of the IEEE International Conference on Communications (ICC’15). IEEE, London, UK, 271--276.Google Scholar
- M. Qin, E. Yaakobi, and P. Siegel. 2014. Constrained codes that mitigate inter-cell interference in read/write cycles for flash memories. IEEE Journal on Selected Areas in Communications. 32, 5 (May 2014), 836--846.Google Scholar
Cross Ref
- K. Park, M. Kang, D. Kim, S. Hwang, B. Choi, Y. Lee, C. Kim, and K. Kim. 2008. A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories. IEEE Journal of Solid State Circuits. 43, 4 (April 2008), 919--928.Google Scholar
Cross Ref
- G. Dong, S. Li, and T. Zhang. 2010. Using data postcompesation and prediction to tolerate cell-to-cell interference in MLC NAND flash memory. IEEE Trans. Circuits and Systems-I Regular Papers. 57, 10 (May 2010), 2718--2728. Google Scholar
Digital Library
- D. Lee and W. Sung. 2012. Least squares based cell-to-cell interference cancelation technique for multi-level cell NAND flash memory. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal (ICASSP’12). IEEE, Kyoto, Japan, 1601--1604.Google Scholar
- S. Joe, M. Jeong, B. Jo, K. Han, S. Park, and J. Lee. 2012. The effect of adjacent bit-line cell interference on random telegraph noise in NAND flash memory cell strings. IEEE Trans. Electron Devices. 59, 12 (December 2012), 3568--3573.Google Scholar
Cross Ref
- T. Kim, G. Kong, X. Weiya, and S. Choi. 2013. Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. IEEE Trans. Magnetics. 49, 6 (June 2013), 2569--2573.Google Scholar
Cross Ref
- S. Chen, B. Ke, J. Chen, and C. Huang. 2011. Reliability analysis and improvement for multi-level non-volatile memories with soft information. In Proceedings of the 18th ACM International Design Automation Conference (DAC’11). ACM, San Diego, CA, USA, 753--758. Google Scholar
Digital Library
- Z. Wang, Z. Cui, and J. Sha. 2011. VLSI design for low-density parity-check code decoding. IEEE Circuits and Systems Magazine. 11, 1 (2011), 52--69.Google Scholar
Cross Ref
- R. Gallager. 1962. Low-density parity-check codes. IRE Trans. Information Theory. 8, 1 (January. 1962), 21--28.Google Scholar
Cross Ref
- D. Lee and W. Sung. 2013. Estimation of NAND flash memory threshold voltage distribution for optimum soft-decision error correction. IEEE Trans. Signal Processing. 61, 2 (2013), 440--449. Google Scholar
Digital Library
- J. Kim, J. Cho, and W. Sung. 2011. A high-speed layered min-sum LDPC decoder for error correction of NAND flash memories. In Proceedings of the IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS’11). IEEE, Seoul, South Korea, 1--4.Google Scholar
- S. Tanakamaru, Y. Yanagihara, and K. Takeuchi. 2012. Over-10x-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC’12). IEEE, San Francisco, CA, USA, 424--426.Google Scholar
- C. Yang, D. Muckatira, A. Kulkarni, and C. Chakrabarti. 2013. Data storage time sensitive ECC schemes for MLC NAND flash memories. In proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP’13). IEEE, Vancouver, Canada, 2513--2517.Google Scholar
- J. Lee, J. Choi, D. Park, and K. Kim. 2003. Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90-nm NAND flash memory. In Proceedings of the 41st IEEE International Reliability Physics Symposium (IRPS’03). IEEE, Dallas, Texas, USA, 497--501.Google Scholar
- J. Zhao, F. Zarkeshvari, and A. Banihashemi. 2005. On implementation of min-sum algorithm and its modifications for decoding low-density parity-check (LDPC) codes. IEEE Trans. Communications. 53, 4 (2005) 549--554.Google Scholar
Cross Ref
- J. Wang, T. Courtade, H. Shankar, and R. Wesel. 2011. Soft information for LDPC decoding in flash: mutual-information optimized quantization. In Proceedings of the IEEE Global Telecommunications Conference (GLOBECOM’11). IEEE, Houston, Texas, USA, 1-6.Google Scholar
- H. Sun, W. Zhao, M. Lv, G. Dong, N. Zheng, and T. Zhang. 2016. Exploiting intracell bit-error characteristics to improve min-sum LDPC decoding for MLC NAND flash-based storage in mobile device. IEEE Trans. Very Large Scale Integration (VLSI) Systems. 24, 8 (2016), 2654--2664.Google Scholar
Digital Library
- X. Hu. 2012. LDPC codes for flash channel. In Proceedings of Flash Memory Summit. Santa Clara, CA, USA.Google Scholar
- P. Huang, P. Subedi, X. He, S. He, and K Zhou. 2014. FlexECC: partially relaxing ECC of MLC SSD for better cache performance. In Proceedings of the USENIX Annual Technical Conference (ATC’14). USENIX, Philadelphia, PA, USA, 489--500. Google Scholar
Digital Library
- J. Meza, Q. Wu, S. Kumar, and O. Mutlu. 2015. A large-scale study of flash memory failures in the field. In Proceedings of the 17st ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS’15). ACM, Portland, Oregon, USA, 177--190. Google Scholar
Digital Library
- S. Gregori, A. Cabrini, O. Khouri, and G. Torelli. 2003. On-chip error correcting techniques for new-generation flash memories. Proceedings of the IEEE. 91, 4 (April 2003), 602--616.Google Scholar
Cross Ref
- J. Kim and W. Sung. 2014. Rate-0.96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory. IEEE Trans. Very Large Scale Integration (VLSI) Systems. 22, 5 (2014), 1004--1015.Google Scholar
Cross Ref
- G. Dong, N. Xie, and T. Zhang. 2010. Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory. In Proceedings of IEEE Globecom Workshops (GC Wkshps’10). IEEE, Miami, FL, USA, 1915--1920.Google Scholar
- L. Qiao, H. Wu, D. Wei, and S. Wang. 2016. A joint decoding strategy of non-binary LDPC codes based on retention error characteristics for MLC NAND flash memories. In Proceedings of the 6th IEEE International Conference on Instrumentation 8 Measurement, Computer, Communication, and Control (IMCCC’16). IEEE, Harbin, China, 183--188.Google Scholar
- C. Aslam, Y. Guan, and K. Cai. 2017. Retention-aware belief-propagation decoding for NAND flash memory. IEEE Trans. Circuits and Systems II: Express Briefs. 64, 6 (2017), 725--729.Google Scholar
Cross Ref
- S. Tanakamaru, Y. Yanagihara, and K. Takeuchi. 2013. Error-prediction LDPC and error-recovery schemes for highly reliable solid-state drives (SSDs). IEEE Journal of Solid State Circuits. 48, 11 (Nov. 2013), 2920--2933.Google Scholar
Cross Ref
- Q. Li, L. Shi, C. Xue, K. Wu, C. Ji, Q. Zhuge, and E. Sha. 2016. Access characteristic guided read and write cost regulation for performance improvement on flash memory. In Proceedings of the 16st USENIX Conference on File and Storage Technologies (FAST’16). USENIX. Santa Clara, CA, USA, 125--132. Google Scholar
Digital Library
- F. Chen, D. Koufaty, and X. Zhang. 2009. Understanding intrinsic characteristics and system implications of flash memory based solid state drives. In Proceedings of the 11st ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS’09). ACM, Seattle, WA, USA, 181--192. Google Scholar
Digital Library
- H. Li, Y. Cao, and J. Dill. 2010. Analysis of error-prone patterns for LDPC codes under belief propagation decoding. In Proceedings of the IEEE Military Communications Conference (MILCOM’10). IEEE, San Jose, CA, USA, 2056--2061.Google Scholar
Index Terms
A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance
Recommendations
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision
Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction ...
Performance Bound for LDPC Coded Unitary Space–Time Modulation
AbstractThis paper is concerned with the bit error probability (BEP) of coded unitary space–time modulation systems based on finite-length low density parity check (LDPC) codes. The union bound on the BEP of the maximum likelihood (ML) decoding is derived ...
LDPC-based Joint Source Channel Coding and Decoding Strategies for single relay cooperative communications
AbstractThis paper investigates new cooperative communication strategies based on Low-Density Parity-Check codes (LDPC) with Joint Source-Channel (JSC) coding and decoding algorithms to efficiently deliver a correlated content to a destination ...






Comments