Abstract
Although the multilevel cell (MLC) technique is widely adopted by flash-memory vendors to boost the chip density and lower the cost, it results in serious performance and reliability problems. Different from past work, a new cell programming method is proposed to not only significantly improve chip performance but also reduce the potential bit error rate. In particular, a single-level cell (SLC)-like programming scheme is proposed to better explore the threshold-voltage relationship to denote different MLC bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in SLC chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming scheme could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for MLC pages.
- Amir Ban. 1995. Flash file system. US Patent 5,404,485.Google Scholar
- Yuan-Hao Chang, Ming-Chang Yang, Tei-Wei Kuo, and Ren-Hung Hwang. 2013. A reliability enhancement design under the flash translation layer for MLC-based flash-memory storage systems. ACM Transactions on Embedded Computing Systems 13, 1, Article 10, 28 pages. Google Scholar
Digital Library
- Yu-Ming Chang, Yuan-Ho Chang, Tei-Wei Kuo, Yung-Chun Li, and Hsiang-Pang Li. 2015. Achieving SLC performance with MLC flash memory. In Proceedings of the 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC’15). Google Scholar
Digital Library
- Chih-Ping Chen, Hang-Ting Lue, Kuo-Pin Chang, Yi-Hsuan Hsaio, Chih-Chang Hsieh, Shih-Hung Chen, Yen-Hao Shih, et al. 2012. A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL). In Proceedings of the 2012 Symposium on VLSI Technology (VLSIT’12).Google Scholar
Cross Ref
- Hyunjin Cho, Dongkun Shin, and Young Ik Eom. 2009. KAST: K-associative sector translation for NAND flash memory in real-time systems. In Proceedings of the 2009 Design, Automation, and Test in Europe Conference and Exhibition (DATE’09). Google Scholar
Digital Library
- Y. S. Cho, I. H. Park, S. Y. Yoon, N. H. Lee, S. H. Joo, K.-W. Song, K. Choi, J.-M. Han, K. H. Kyung, and Y.-H. Jun. 2013. Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH. IEEE Journal of Solid-State Circuits 48, 4, 948--959.0018-9200Google Scholar
Cross Ref
- Ki-Tae Park, Jin-Man Han, Daehan Kim, Sangwan Nam, Kihwan Choi, Min-Su Kim, Pansuk Kwak, et al. 2014. 19.5 Three-dimensional 128Gb MLC vertical NAND flash-memory with 24-WL stacked layers and 50MB/s high-speed programming. In Proceedings of the 2014 IEEE International Solid-State Circuits Digest of Technical Papers (ISSCC’14). 334--335.Google Scholar
Cross Ref
- C. Monzio Compagnoni, M. Ghidotti, A. L. Lacaita, A. S. Spinelli, and A. Visconti. 2009. Random telegraph noise effect on the programmed threshold-voltage distribution of flash memories. IEEE Electron Device Letters 30, 9, 984--986.Google Scholar
Cross Ref
- TPC. 2018. TPC-C Benchmark Revision 5.10.1. Available at http://www.tpc.org/tpcc/.Google Scholar
- Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, and Jack K. Wolf. 2009. Characterizing flash memory: Anomalies, observations, and applications. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’09). Google Scholar
Digital Library
- Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XIV). 229--240. Google Scholar
Digital Library
- Soojun Im and Dongkun Shin. 2011. Flash-aware RAID techniques for dependable and high-performance flash memory SSD. IEEE Transactions on Computers 60, 1, 80--92. Google Scholar
Digital Library
- A. Jagmohan, M. Franceschini, and L. Lastras. 2010. Write amplification reduction in NAND flash through multi-write coding. In Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST’10). Google Scholar
Digital Library
- J. Kim, J. M. Kim, S. H. Noh, S.-L. Min, and Y. Cho. 2002. A space-efficient flash translation layer for CompactFlash systems. IEEE Transactions on Consumer Electronics 48, 2, 366--375. 0098-3063 Google Scholar
Digital Library
- Sang-Won Lee, Won-Kyoung Choi, and Dong-Joo Park. 2006. FAST: An efficient flash translation layer for flash memory. In Proceedings of the International Conference on Embedded and Ubiquitous Computing (EUC’06). 879--887. Google Scholar
Digital Library
- Chih-Yuan Lu, Kuang-Yeu Hsieh, and Rich Liu. 2007. Future challenges of flash memory technologies. In Proceedings of the International Symposium on Advanced Gate Stack Technology (ISAGST’07).Google Scholar
- Ki-Tae Park, Myounggon Kang, Doogon Kim, Soon-Wook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, and Kinam Kim. 2008. A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories. IEEE Journal of Solid-State Circuits 43, 4, 919--928.Google Scholar
Cross Ref
- Sang-Hoon Park, Seung-Hwan Ha, Kwanhu Bang, and Eui-Young Chung. 2009. Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices. IEEE Transactions on Consumer Electronics 55, 3, 1392--1400. Google Scholar
Digital Library
- Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, and Yong Guan. 2011. MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems. In Proceedings of the 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC’11). Google Scholar
Digital Library
- South Korea Samsung. 2014. Samsung K90KGY8S7C-CCK0 32 Layer Gen 2 3D NAND Flash.Google Scholar
- Seung-Hwan Shin, Dong-Kyo Shim, Jae-Yong Jeong, Oh-Suk Kwon, Sang-Yong Yoon, Myung-Hoon Choi, Tae-Young Kim, et al. 2012. A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. In Proceedings of the 2012 Symposium on VLSI Circuits (VLSIC’12).Google Scholar
Cross Ref
- YunSeung Shin. 2005. Non-volatile memory technologies for beyond 2010. In Proceedings of the 2005 Symposium on VLSI Circuits (VLSIC’05).Google Scholar
- Takayuki Shinohara. 1999. Flash memory card with block memory address arrangement. US Patent 5,905,993.Google Scholar
- Kang-Deog Suh, Byung-Hoon Suh, Young-Ho Lim, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung-Soo Lee, et al. 1995. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE Journal of Solid-State Circuits 30, 11, 1149--1156.Google Scholar
Cross Ref
- H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, et al. 2007. Bit cost scalable technology with punch and plug process for ultra high density flash memory. In Proceedings of the 2007 IEEE Symposium on VLSI Technology (VLSIT’07).Google Scholar
Cross Ref
- Japan Toshiba, Tokyo. 2012. Toshiba MOS digital integrated circuit silicon gate CMOS, 19nm 32Gbit TLC TC58TEG5T2JTA00 NAND Flash.Google Scholar
- Exchange Trace. 2010. SNIA IOTTA Repository. http://iotta.snia.org/traces/130.Google Scholar
- Qingsong Wei, Bozhao Gong, Suraj Pathak, Bharadwaj Veeravalli, LingFang Zeng, and Kanzo Okada. 2011. WAFTL: A workload adaptive flash translation layer with data partition. In Proceedings of the 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST’11). Google Scholar
Digital Library
- Chin-Hsien Wu and Tei-Wei Kuo. 2006. An adaptive two-level management for the flash translation layer in embedded systems. In Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’06). Google Scholar
Digital Library
Index Terms
An SLC-Like Programming Scheme for MLC Flash Memory
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