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Integrating task scheduling and cache locking for multicore real-time embedded systems

Published:21 June 2017Publication History
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Abstract

Modern embedded processors provide hardware support for cache locking, a mechanism used to facilitate the WCET (Worst-Case Execution Time) calculation of a task. We investigate the problem of integrating task scheduling and cache locking for a set of preemptible tasks with individual release times and deadlines on a multi-core processor with two-level caches. We propose a novel integrated approach that schedules the task set and allocates the locked cache contents of each task to the local caches (L1 caches) and the level-two cache (L2 cache). Our approach consists of three major components, the task scheduler, the L1 cache allocator, and the L2 cache allocator. The task scheduler aims at minimizing the number of task preemptions. The L1 cache allocator converts the interference graph of all the tasks scheduled on each core into a DAG by considering the preemptions between tasks and allocates the L1 cache space to each task. The L2 cache allocator converts the interference graph of all the tasks into a DAG by using a k-longest-path-based graph orientation algorithm and allocates the L2 cache space to each task. Both cache allocators significantly improve the cache utilization for all the caches due to the efficient use of the interference graphs of tasks. We have implemented our approach and compared it with the extended version of the preemption tree-based approach and the static analysis approach without cache locking by using a set of benchmarks from the MRTC WCET benchmark suite and SNU real-time benchmarks. Compared to the extended version of the preemption tree-based approach, the maximum WCRT (Worst Case Response Time) improvement of our approach is 15%. Compared to the static analysis approach, the maximum WCRT improvement of our approach is 37%.

References

  1. Snu real-time benchmarks. http://archi.snu.ac.kr/realtime/ benchmark/.Google ScholarGoogle Scholar
  2. D. Burger and T. M. Austin. The simplescalar tool set, version 2.0. ACM SIGARCH Computer Architecture News, 25(3):13–25, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. J. V. Busquets-Mataix, J. J. Serrano-Martin, R. Ors-Carot, P. Gil, and A. Wellings. Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems. In Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, pages 271–276. IEEE, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. A. M. Campoy, A. Ivars, and J. Busquets-Mataix. Using genetic algorithms in content selection for locking-caches. In Proceedings of the international symposium on applied informatics, pages 271–276, 2001.Google ScholarGoogle Scholar
  5. A. M. Campoy, A. P. Ivars, and J. Busquets-Mataix. Dynamic use of locking caches in multitask, preemptive real-time systems. In Proceedings of the 15th Triennial World Congress of the International Federation of Automatic Control, 2002.Google ScholarGoogle ScholarCross RefCross Ref
  6. H. Ding, Y. Liang, and T. Mitra. Shared cache aware task mapping for wcrt minimization. In Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, pages 735–740. IEEE, 2013.Google ScholarGoogle Scholar
  7. H. Ding, Y. Liang, and T. Mitra. Wcet-centric dynamic instruction cache locking. In Proceedings of the conference on Design, Automation & Test in Europe, pages 1–6. IEEE, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. H. Falk, S. Plazar, and H. Theiling. Compile-time decided instruction cache locking using worst-case execution paths. In Proceedings of the 5th international conference on Hardware/software codesign and system synthesis, pages 143–148. ACM, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. The mälardalen wcet benchmarks: Past, present and future. In the 10th International Workshop on Worst-Case Execution Time Analysis (WCET’10), pages 136–146, 2010.Google ScholarGoogle Scholar
  10. J. C. Kleinsorge, H. Falk, and P. Marwedel. A synergetic approach to accurate analysis of cache-related preemption delay. In Proceedings of the ninth international conference on Embedded software, pages 329–338. ACM, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. X. Li, Y. Liang, T. Mitra, and A. Roychoudhury. Chronos: A timing analyzer for embedded software. Science of Computer Programming, pages 56–67, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Y. Liang, H. Ding, T. Mitra, A. Roychoudhury, Y. Li, and V. Suhendra. Timing analysis of concurrent programs running on shared cache multi-cores. Real-Time Systems, 48(6):638–680, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. T. Liu, M. Li, and C. J. Xue. Minimizing wcet for real-time embedded systems via static instruction cache locking. In Real-Time and Embedded Technology and Applications Symposium, 2009. RTAS 2009. 15th IEEE, pages 35–44. IEEE, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. T. Liu, Y. Zhao, M. Li, and C. J. Xue. Task assignment with cache partitioning and locking for wcet minimization on mpsoc. In Parallel Processing (ICPP), 2010 39th International Conference on, pages 573–582. IEEE, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. T. Liu, M. Li, and C. J. Xue. Instruction cache locking for multitask real-time embedded systems. Real-Time Systems, 48(2):166–197, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. S. Plazar, J. C. Kleinsorge, P. Marwedel, and H. Falk. Wcet-aware static locking of instruction caches. In Proceedings of the Tenth International Symposium on Code Generation and Optimization, pages 44–52. ACM, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. I. Puaut and A. Arnaud. Dynamic instruction cache locking in hard real-time systems. In Proceedings of the 14th International Conference on Real-Time and Network Systems, 2006.Google ScholarGoogle Scholar
  18. I. Puaut and D. Decotigny. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Proceedings of the 23rd IEEE Real-Time Systems Symposium, pages 114–123. IEEE, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. H. Salamy and J. Ramanujam. A framework for task scheduling and memory partitioning for multi-processor system-on-chip. In High Performance Embedded Architectures and Compilers, pages 263–277. Springer, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. V. Suhendra and T. Mitra. Exploring locking & partitioning for predictable shared caches on multi-cores. In Proceedings of the 45th annual Design Automation Conference, pages 300–303. ACM, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. V. Suhendra, C. Raghavan, and T. Mitra. Integrated scratchpad memory optimization and task scheduling for mpsoc architectures. In Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pages 401–410. ACM, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. X. Vera, B. Lisper, and J. Xue. Data cache locking for higher program predictability. In ACM SIGMETRICS Performance Evaluation Review, volume 31, pages 272–282. ACM, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Q. Wan, H. Wu, and J. Xue. Scratchpad memory aware task scheduling with minimum number of preemptions on a single processor. In Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, pages 741–748, Jan 2013..Google ScholarGoogle Scholar
  24. W. Zheng and H. Wu. Wcet aware dynamic instruction cache locking. In Proceedings of the conference on Languages, compilers and tools for embedded systems, pages 53–62. ACM, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. W. Zheng and H. Wu. Wcet-aware dynamic d-cache locking for a single task. In Proceedings of the 16th Languages, Compilers and Tools for Embedded Systems, pages 8:1–8:10. ACM, 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 52, Issue 5
      LCTES '17
      May 2017
      120 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/3140582
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES 2017: Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems
        June 2017
        120 pages
        ISBN:9781450350303
        DOI:10.1145/3078633
        • General Chair:
        • Vijay Nagarajan,
        • Program Chair:
        • Zili Shao

      Copyright © 2017 ACM

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 21 June 2017

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