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Transactions in relaxed memory architectures

Published:27 December 2017Publication History
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Abstract

The integration of transactions into hardware relaxed memory architectures is a topic of current research both in industry and academia. In this paper, we provide a general architectural framework for the introduction of transactions into models of relaxed memory in hardware, including the SC, TSO, ARMv8 and PPC models. Our framework incorporates flexible and expressive forms of transaction aborts and execution that have hitherto been in the realm of software transactional memory. In contrast to software transactional memory, we account for the characteristics of relaxed memory as a restricted form of distributed system, without a notion of global time. We prove abstraction theorems to demonstrate that the programmer API matches the intuitions and expectations about transactions.

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        cover image Proceedings of the ACM on Programming Languages
        Proceedings of the ACM on Programming Languages  Volume 2, Issue POPL
        January 2018
        1961 pages
        EISSN:2475-1421
        DOI:10.1145/3177123
        Issue’s Table of Contents

        Copyright © 2017 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 27 December 2017
        Published in pacmpl Volume 2, Issue POPL

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