Abstract
Phase Change Memory (PCM) has drawn great attention as a main memory due to its attractive characteristics such as non-volatility, byte-addressability, and in-place update. However, since the capacity of PCM is not fully mature yet, hybrid memory architecture that consists of DRAM and PCM has been suggested as a main memory. In addition, page replacement algorithm based on hybrid memory architecture is actively being studied, because existing page replacement algorithms cannot be used on hybrid memory architecture in that they do not consider the two weaknesses of PCM: high write latency and low endurance. In this article, to mitigate the above hardware limitations of PCM, we revisit the page cache layer for the hybrid memory architecture and propose a novel page replacement algorithm, called M-CLOCK, to improve the performance of hybrid memory architecture and the lifespan of PCM. In particular, M-CLOCK aims to reduce the number of PCM writes that negatively affect the performance of hybrid memory architecture. Experimental results clearly show that M-CLOCK outperforms the state-of-the-art page replacement algorithms in terms of the number of PCM writes and effective memory access time by up to 98% and 9.4 times, respectively.
- Xianzhang Chen, Edwin H.-M. Sha, Weiwen Jiang, Qingfeng Zhuge, Junxi Chen, Jiejie Qin, and Yuansong Zeng. 2016. The design of an efficient swap mechanism for hybrid DRAM-NVM systems. In Proceedings of the IEEE International Conference on Embedded Software (EMSOFT’16). ACM, 1--10. Google Scholar
Digital Library
- Hoeju Chung, Byung Hoon Jeong, and Byungjun Min. 2011. A58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC’11). IEEE, 500--502.Google Scholar
- Gaurav Dhiman, Raid Ayoub, and Tajana Rosing. 2009. PDRAM: A hybrid PRAM and DRAM main memory system. In Proceedings of the Design Automation Conference (DAC’09). IEEE, 664--669. Google Scholar
Digital Library
- Subramanya R. Dulloor, Amitabha Roy, Zheguang Zhao, Narayanan Sundaram, Nadathur Satish, Rajesh Sankaran, Jeff Jackson, and Karsten Schwan. 2016. Data tiering in heterogeneous memory systems. In Proceedings of the European Conference on Computer Systems (EuroSys’16). ACM, 1--16. Google Scholar
Digital Library
- Sean Eilert, Mark Leinwander, and Giuseppe Crisenza. 2009. Phase change memory: A new memory enables new memory usage models. In Proceedings of the International Memory Workshop (IMW’09). IEEE, 1--2.Google Scholar
Cross Ref
- Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem, and Daniel Mossé. 2010. Increasing PCM main memory lifetime. In Proceedings of the Design, Automation and Test in Europe (DATE’10). European Design and Automation Association, 914--919. Google Scholar
Digital Library
- Song Jiang, Feng Chen, and Xiaodong Zhang. 2005. CLOCK-Pro: An effective improvement of the clock replacement. In Proceedings of the USENIX Annual Technical Conference (ATC’05). USENIX, 323--336. Google Scholar
Digital Library
- Dong Hyun Kang and Young Ik Eom. 2016. FSLRU: A page cache algorithm for mobile devices with hybrid memory architecture. IEEE Trans. Cons. Electron. 62, 2 (2016), 136--143. Google Scholar
Digital Library
- Dongki Kim, Sungkwang Lee, Jaewoong Chung, Dae Hyun Kim, Dong Hyuk Woo, Sungjoo Yoo, and Sunggu Lee. 2012. Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU. In Proceedings of the Design Automation Conference (DAC’12). ACM, 888--896. Google Scholar
Digital Library
- Hyojun Kim, Sangeetha Seshadri, Clement L. Dickey, and Lawrence Chiu. 2014. Evaluating phase change memory for enterprise storage systems: A study of caching and tiering approaches. In Proceedings of the USENIX Conference on File and Storage Technologies. USENIX, 33--45. Google Scholar
Digital Library
- Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, and Doug Burger. 2010. Phase change technology and the future of main memory. IEEE Micro 30, 1 (2010), 131--141. Google Scholar
Digital Library
- Eunji Lee, Julie Kim, Hyokyung Bahn, and Sam H. Noh. 2016. Reducing write amplification of flash storage through cooperative data management with NVM. In Proceedings of the IEEE International Conference on Massive Data Storage Systems and Technology (MSST’16). IEEE, 1--6.Google Scholar
- Soyoon Lee, Hyokyung Bahn, and S. Noh. 2013. CLOCK-DWF: A write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures. IEEE Trans. Comput. 63, 9 (2013), 1--14. Google Scholar
Digital Library
- Taemin Lee, Dongki Kim, and Hyunsun Park. 2014. FPGA-based prototyping systems for emerging memory technologies. In Proceedings of the IEEE International Symposium on Rapid System Prototyping (RSP’14). IEEE, 115--120.Google Scholar
Cross Ref
- Ye-jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, and Cheng-Yuan Michael Wang. 2015. A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. In Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium (NVMSA’15). IEEE, 1--6.Google Scholar
- Jeffrey C. Mogul, Eduardo Argollo, Mehul Shah, and Paolo Faraboschi. 2009. Operating system support for NVM+DRAM hybrid main memory. In Proceedings of the USENIX Hot Topics in Operating Systems (HotOS’09). USENIX, 1--5. Google Scholar
Digital Library
- Nicholas Nethercote and Julian Seward. 2003. Valgrind: A program supervision framework. Electr. Not. Theoret. Comput. Sci. 89, 2 (2003), 44--66.Google Scholar
Cross Ref
- Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase change memory technology. ACM SIGARCH Comput. Arch. News 37, 3 (2009), 24--33. Google Scholar
Digital Library
- Luiz E. Ramos, Eugene Gorbatov, and Ricardo Bianchini. 2012. Page placement in hybrid memory systems. In Proceedings of International Conference on Supercomputing (ICS’12). ACM, 95--95. Google Scholar
Digital Library
- Hyunchul Seok, Youngwoo Park, Ki-Woong Park, and Kyu Ho Park. 2011. Efficient page caching algorithm with prediction and migration for a hybrid main memory. ACM SIGAPP Appl. Comput. Rev. 11, 4 (2011), 38--48. Google Scholar
Digital Library
- Andrew S. Tanenbaum and Albert S. Woodhull. 1987. Operating Systems: Design and Implementation. Prentice-Hall Englewood Cliffs, NJ. Google Scholar
Digital Library
- Wikipedia. 2014. Memory Refresh. Retrieved from http://en.wikipedia.org/wiki/Memory_refresh/.Google Scholar
- HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael A. Harding, and Onur Mutlu. 2012. Row buffer locality aware caching policies for hybrid memories. In Proceedings of the International Conference on Computer Design (ICCD’12). IEEE, 337--344. Google Scholar
Digital Library
- Kan Zhong, Tianzheng Wang, Xiao Zhu, Linho Long, Duo Liu, Weichen Liu, Zili Shao, and Edwin H.-M. Sha. 2014. Building high-performance smartphones via non-volatile memory: The swap approach. In Proceedings of the IEEE International Conference on Embedded Software (EMSOFT’14). ACM, 1--10. Google Scholar
Digital Library
- Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. ACM SIGARCH Comput. Arch. News 37, 3 (2009), 14--23. Google Scholar
Digital Library
Index Terms
M-CLOCK: Migration-optimized Page Replacement Algorithm for Hybrid Memory Architecture
Recommendations
M-CLOCK: migration-optimized page replacement algorithm for hybrid DRAM and PCM memory architecture
SAC '15: Proceedings of the 30th Annual ACM Symposium on Applied ComputingPhase Change Memory (PCM) has drawn great attention as a main memory due to its attractive characteristics such as non-volatility, byte-addressability, and in-place update. However, since the capacity of PCM is not fully mature yet, hybrid memory ...
A Novel Memory Block Management Scheme for PCM Using WOM-Code
HPCC-CSS-ICESS '15: Proceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and SystemsPhase Change Memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics including low static power consumption and high density. However, long write latency is one of the major drawbacks in current PCM ...
Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
Nonvolatile memories such as Flash memory, phase change memory (PCM), and magnetic random access memory (MRAM) have many desirable characteristics for embedded systems to employ them as main memory. However, there are two common challenges we need to ...






Comments