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Automated Synthesis of Streaming Transfer Level Hardware Designs

Published:09 November 2018Publication History
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Abstract

As modern field-programmable gate arrays (FPGA) enable high computing performance and efficiency, their programming with low-level hardware description languages is time-consuming and remains a major obstacle to their adoption. High-level synthesis compilers are able to produce register-transfer-level (RTL) designs from C/C++ algorithmic descriptions, but despite allowing significant design-time improvements, these tools are not always able to generate hardware designs that compare to handmade RTL designs. In this article, we consider synthesis from an intermediate-level (IL) language that allows the description of algorithmic state machines handling connections between streaming sources and sinks. However, the interconnection of streaming sources and sinks can lead to cyclic combinational relations, resulting in undesirable behaviors or un-synthesizable designs. We propose a functional-level methodology to automate the resolution of such cyclic relations into acyclic combinational functions. The proposed IL synthesis methodology has been applied to the design of pipelined floating-point cores. The results obtained show how the proposed IL methodology can simplify the description of pipelined architectures while enabling performances that are close to those achievable through an RTL design methodology.

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  1. Automated Synthesis of Streaming Transfer Level Hardware Designs

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              • Published in

                cover image ACM Transactions on Reconfigurable Technology and Systems
                ACM Transactions on Reconfigurable Technology and Systems  Volume 11, Issue 2
                June 2018
                109 pages
                ISSN:1936-7406
                EISSN:1936-7414
                DOI:10.1145/3242893
                • Editor:
                • Steve Wilton
                Issue’s Table of Contents

                Copyright © 2018 ACM

                Publisher

                Association for Computing Machinery

                New York, NY, United States

                Publication History

                • Published: 9 November 2018
                • Accepted: 1 July 2018
                • Revised: 1 June 2018
                • Received: 1 May 2017
                Published in trets Volume 11, Issue 2

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