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Efficient sparsification of dense circuit matrices in model order reduction

Published:21 January 2019Publication History

ABSTRACT

The integration of more components into ICs due to the ever increasing technology scaling has led to very large parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

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  • Published in

    cover image ACM Conferences
    ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
    January 2019
    794 pages
    ISBN:9781450360074
    DOI:10.1145/3287624

    Copyright © 2019 ACM

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    New York, NY, United States

    Publication History

    • Published: 21 January 2019

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