Abstract
Resource management strategies for many-core systems need to enable sharing of resources such as power, processing cores, and memory bandwidth while coordinating the priority and significance of system- and application-level objectives at runtime in a scalable and robust manner. State-of-the-art approaches use heuristics or machine learning for resource management, but unfortunately lack formalism in providing robustness against unexpected corner cases. While recent efforts deploy classical control-theoretic approaches with some guarantees and formalism, they lack scalability and autonomy to meet changing runtime goals. We present SPECTR, a new resource management approach for many-core systems that leverages formal supervisory control theory (SCT) to combine the strengths of classical control theory with state-of-the-art heuristic approaches to efficiently meet changing runtime goals. SPECTR is a scalable and robust control architecture and a systematic design flow for hierarchical control of many-core systems. SPECTR leverages SCT techniques such as gain scheduling to allow autonomy for individual controllers. It facilitates automatic synthesis of the high-level supervisory controller and its property verification. We implement SPECTR on an Exynos platform containing ARM»s big.LITTLE-based heterogeneous multi-processor (HMP) and demonstrate that SPECTR»s use of SCT is key to managing multiple interacting resources (e.g., chip power and processing cores) in the presence of competing objectives (e.g., satisfying QoS vs. power capping). The principles of SPECTR are easily applicable to any resource type and objective as long as the management problem can be modeled using dynamical systems theory (e.g., difference equations), discrete-event dynamic systems, or fuzzy dynamics.
- K. Akesson, M. Fabian, H. Flordal, and R. Malik, "Supremica - An integrated environment for veriication, synthesis and simulation of discrete event systems," in WODES 2006.Google Scholar
- ARM, "big.LITTLE Technology: The Future of Mobile," Tech. Rep., 2013. {Online}. Available: https://www.arm.com/iles/pdf/big_LITTLE_Technology_the_Futue_ of_Mobile.pdfGoogle Scholar
- K. J. Astrom and B. Wittenmark, Adaptive Control. Addison-Wesley, 1995. Google Scholar
Digital Library
- A. Bartolini, M. Cacciari, A. Tilli, and L. Benini, "A distributed and selfcalibrating model-predictive controller for energy and thermal management of high-performance multicores," in DATE, 2011.Google Scholar
- M. W. Bertil A. Brandin and B. Benhabib, "Discrete Event System Supervisory Control Applied to the Management of Manufacturing Workcells," in Computer- Aided Production Engineering, C. Venkatesh and J.A. McGeough, eds. (Amsterdam: Elsevier), 1991.Google Scholar
- C. Bienia, "Benchmarking modern multiprocessors," Ph.D. dissertation, Princeton University, 2011. Google Scholar
Digital Library
- R. Bitirgen, E. Ipek, and J. F. Martinez, "Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach," in MICRO, 2008. Google Scholar
Digital Library
- J. Buerger and M. Cannon, "Nonlinear MPC for supervisory control of hybrid electric vehicles," in ECC, 2016.Google Scholar
- K. K. Chang, A. G. Yağlıkçı, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O'Connor, H. Hassan, and O. Mutlu, "Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms," Proc. ACM Meas. Anal. Comput. Syst., 2017. Google Scholar
Digital Library
- S. Choi and D. Yeung, "Learning-Based SMT Processor Resource Distribution via Hill-Climbing," in ISCA, 2006. Google Scholar
Digital Library
- R. Cochran, C. Hankendi, A. K. Coskun, and S. Reda, "Pack&Cap: Adaptive DVFS and Thread Packing Under Power Caps," in MICRO, 2011. Google Scholar
Digital Library
- R. Das, R. Ausavarungnirun, O. Mutlu, A. Kumar, and M. Azimi, "Applicationto- core mapping policies to reduce memory system interference in multi-core systems," in HPCA, 2013. Google Scholar
Digital Library
- R. Das, O. Mutlu, T. Moscibroda, and C. R. Das, "Application-aware prioritization mechanisms for on-chip networks," in MICRO, 2009. Google Scholar
Digital Library
- R. Das, O. Mutlu, T. Moscibroda, and C. R. Das, "AéRgia: Exploiting Packet Latency Slack in On-chip Networks," in ISCA, 2010. Google Scholar
Digital Library
- H. David, C. Fallin, E. Gorbatov, U. R. Hanebutte, and O. Mutlu, "Memory power management via dynamic voltage/frequency scaling," in ICAC, 2011. Google Scholar
Digital Library
- C. Delimitrou and C. Kozyrakis, "Quasar: Resource-eicient and QoS-aware Cluster Management," in ASPLOS, 2014. Google Scholar
Digital Library
- Q. Deng, D. Meisner, A. Bhattacharjee, T. F. Wenisch, and R. Bianchini, "CoScale: Coordinating CPU and Memory System DVFS in Server Systems," in MICRO, 2012. Google Scholar
Digital Library
- A. S. Dhodapkar and J. E. Smith, "Managing Multi-coniguration Hardware via Dynamic Working Set Analysis," in ISCA, 2002. Google Scholar
Digital Library
- B. Donyanavard, T. Mück, S. Sarma, and N. Dutt, "Sparta: Runtime task allocation for energy eicient heterogeneous many-cores," in CODES, 2016. Google Scholar
Digital Library
- C. Dubach, T. M. Jones, and E. V. Bonilla, "Dynamic Microarchitectural Adaptation Using Machine Learning," in TACO, 2013. Google Scholar
Digital Library
- C. Dubach, T. M. Jones, E. V. Bonilla, and M. F. P. O'Boyle, "A Predictive Model for Dynamic Microarchitectural Adaptivity Control," in MICRO, 2010. Google Scholar
Digital Library
- J. Eaton, D. Bateman, S. Hauberg, and R.Wehbring, GNU Octave version 3.8.1 manual: a high-level interactive language for numerical computations. CreateSpace Independent Publishing Platform, 2014.Google Scholar
- E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt, "Prefetch-aware shared-resource management for multi-core systems," in ISCA, 2011. Google Scholar
Digital Library
- E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt, "Fairness via source throttling: A conigurable and high-performance fairness substrate for multi-core memory systems," in ASPLOS, 2010. Google Scholar
Digital Library
- E. Ebrahimi, O. Mutlu, C. J. Lee, and Y. N. Patt, "Coordinated Control of Multiple Prefetchers in Multi-core Systems," in MICRO, 2009. Google Scholar
Digital Library
- L. P. Eric Walter, Identiication of Parametric Models from experimental results. Springer, 1997.Google Scholar
- M. Fabian and A. Hellgren, Desco Ð a Tool for Education and Control of Discrete Event Systems. Springer, 2000.Google Scholar
Cross Ref
- S. Fan, S. M. Zahedi, and B. C. Lee, "The Computational Sprinting Game," in ASPLOS, 2016. Google Scholar
Digital Library
- X. Fu, K. Kabir, and X. Wang, "Cache-Aware Utilization Control for Energy Eiciency in Multi-Core Real-Time Systems," in ECRTS, 2011. Google Scholar
Digital Library
- P. Greenhalgh, "Big. little processing with arm cortex-a15&cortex-a7," in ARM White paper, 2011.Google Scholar
- U. Gupta, R. Ayoub, M. Kishinevsky, D. Kadjo, N. Soundararajan, U. Tursun, and U. Ogras, "Dynamic Power Budgeting for Mobile Systems Running Graphics Workloads," in TMSCS, 2017.Google Scholar
- U. Gupta, J. Campbell, U. Y. Ogras, R. Ayoub, M. Kishinevsky, F. Paterna, and S. Gumussoy, "Adaptive performance prediction for integrated GPUs," in ICCAD, 2016. Google Scholar
Digital Library
- M. H. Haghbayan, A. Miele, A. M. Rahmani, P. Liljeberg, and H. Tenhunen, "Performance/Reliability-Aware Resource Management for Many-Cores in Dark Silicon Era," IEEE Transactions on Computers, 2017.Google Scholar
- V. Hanumaiah, D. Desai, B. Gaudette, C.-J. Wu, and S. Vrudhula, "STEAM: A Smart Temperature and Energy Aware Multicore Controller," in TECS, 2014. Google Scholar
Digital Library
- Hardkernel, "ODROID-XU," Tech. Rep. {Online}. Available: http://www. hardkernel.com/main/main.phpGoogle Scholar
- J. L. Hellerstein, Y. Diao, S. Parekh, and D. M. Tilbury, Feedback Control of Computing Systems. John Wiley&Sons, 2004. Google Scholar
Digital Library
- J. P. Hespanha, "Tutorial on supervisory control," in Lecture Notes for the workshop Control using Logic and Switching for the 40th Conference on Decision and Control, 2011.Google Scholar
- H. Hofmann, "Coadapt: Predictable behavior for accuracy-aware applications running on power-aware systems," in ECRTS, 2014. Google Scholar
Digital Library
- H. Hofmann, M. Maggio, M. D. Santambrogio, A. Leva, and A. Agarwal, "A generalized software framework for accurate and eicient management of performance goals," in EMSOFT, 2013. Google Scholar
Digital Library
- H. Hofmann, S. Sidiroglou, M. Carbin, S. Misailovic, A. Agarwal, and M. Rinard, "Dynamic Knobs for Responsive Power-aware Computing," in ASPLOS, 2011. Google Scholar
Digital Library
- J. E. Hopcroft and J. D. Ullman, Introduction to Automata Theory, Languages, and Computation. Addison-Wesley, 1979. Google Scholar
Digital Library
- Q. Hui,W. Qiao, and C. Peng, "Neuromorphic-computing-based feedback control: A cognitive supervisory control framework," in CDC, 2016.Google Scholar
- E. Ipek, O. Mutlu, J. F. Martínez, and R. Caruana, "Self-Optimizing Memory Controllers: A Reinforcement Learning Approach," in ISCA, 2008. Google Scholar
Digital Library
- C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An Analysis of Eicient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget," in MICRO, 2006. Google Scholar
Digital Library
- P. Juang, Q. Wu, L.-S. Peh, M. Martonosi, and D. W. Clark, "Coordinated, distributed, formal energy management of chip multiprocessors," in ISLPED, 2005. Google Scholar
Digital Library
- H. Jung, P. Rong, and M. Pedram, "Stochastic modeling of a thermally-managed multi-core system," in DAC, 2008. Google Scholar
Digital Library
- D. Kadjo, R. Ayoub, M. Kishinevsky, and P. V. Gratz, "A Control-theoretic Approach for Energy Eicient CPU-GPU Subsystem in Mobile Platforms," in DAC, 2015. Google Scholar
Digital Library
- A. Kanduri, M. H. Haghbayan, A. M. Rahmani, P. Liljeberg, A. Jantsch, N. Dutt, and H. Tenhunen, "Approximation knob: Power Capping meets energy eiciency," in ICCAD, 2016. Google Scholar
Digital Library
- C. Karamanolis, M. Karlsson, and X. Zhu, "Designing Controllable Computer Systems," in HoTOS, 2005. Google Scholar
Digital Library
- C. J. Lee, V. Narasiman, E. Ebrahimi, O. Mutlu, and Y. N. Patt, "DRAM-aware lastlevel cache writeback: Reducing write-caused interference in memory systems," UT Austin, Tech. Rep., 2010.Google Scholar
- D. Leith and W. Leithead, "Survey of gain-scheduling analysis and design," in International Journal of Control, 2000.Google Scholar
- L. Ljung, "Black-box models from input-output measurements," in I2MTC, 2001.Google Scholar
- L. Ljung, System Identiication: Theory for the User. Prentice Hall PTR, 1999. Google Scholar
Digital Library
- D. Lo, T. Song, and G. E. Suh, "Prediction-guided Performance-energy Trade-of for Interactive Applications," in MICRO, 2015. Google Scholar
Digital Library
- K. Ma, X. Li, M. Chen, and X. Wang, "Scalable power control for many-core architectures running multi-threaded applications," in ISCA, 2011. Google Scholar
Digital Library
- M. Maggio, H. Hofmann, M. D. Santambrogio, A. Agarwal, and A. Leva, "Controlling software applications via resource allocation within the heartbeats framework, " in CDC, 2010.Google Scholar
- D. Mahajan, A. Yazdanbakhsh, J. Park, B. Thwaites, and H. Esmaeilzadeh, "Towards Statistical Guarantees in Controlling Quality Tradeofs for Approximate Acceleration," in ISCA, 2016. Google Scholar
Digital Library
- F. Maraninchi, "Operational and Compositional Semantics of Synchronous Automaton Compositions ," in CONCUR, 1992, aug. Google Scholar
Digital Library
- MathWorks, "System Identiication Toolbox," Tech. Rep., 2017. {Online}. Available: https://www.mathworks.com/products/sysid.htmlGoogle Scholar
- A. K. Mishra, S. Srikantaiah, M. Kandemir, and C. R. Das, "CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors," in SC, 2010. Google Scholar
Digital Library
- S. Morse, Control using logic-based switching. Springer, 1997. Google Scholar
Digital Library
- T. S. Muthukaruppan, A. Pathania, and T. Mitra, "Price Theory Based Power Management for Heterogeneous Multi-cores," in ASPLOS, 2014.Google Scholar
- T. S. Muthukaruppan, M. Pricopi, V. Venkataramani, T. Mitra, and S. Vishin, "Hierarchical Power Management for Asymmetric Multi-core in Dark Silicon Era," in DAC, 2013. Google Scholar
Digital Library
- NIST, "Engineering Statistics Handbook," Tech. Rep. {Online}. Available: http://www.itl.nist.gov/div898/handbook/index.htmGoogle Scholar
- P. Petrica, A. M. Izraelevitz, D. H. Albonesi, and C. A. Shoemaker, "Flicker: A Dynamically Adaptive Architecture for Power Limited Multicore Systems," in ISCA, 2013. Google Scholar
Digital Library
- R. P. Pothukuchi, A. Ansari, P. Voulgaris, and J. Torrellas, "Using Multiple Input, Multiple Output Formal Control to Maximize Resource Eiciency in Architectures, " in ISCA, 2016. Google Scholar
Digital Library
- R. P. Pothukuchi and J. Torrellas, "A Guide to Design MIMO Controllers for Architectures," in http://iacoma.cs.uiuc.edu/iacoma-papers/mimoTR.pdf.Google Scholar
- Q. Wu, P. Juang, M. Martonosi, D. W. Clark, "Formal Online Methods for Voltage/ Frequency Control in Multiple Clock Domain Microprocessors," in ASPLOS, 2004. Google Scholar
Digital Library
- R. Raghavendra, P. Ranganathan, V. Talwar, Z. Wang, and X. Zhu, "No "Power" Struggles: Coordinated Multi-level Power Management for the Data Center," in ISCA, 2008.Google Scholar
- A. M. Rahmani, M. H. Haghbayan, A. Kanduri, A. Y. Weldezion, P. Liljeberg, J. Plosila, A. Jantsch, and H. Tenhunen, "Dynamic power management for manycore platforms in the dark silicon era: A multi-objective control approach," in ISLPED, 2015.Google Scholar
- A. M. Rahmani, M. H. Haghbayan, A. Miele, P. Liljeberg, A. Jantsch, and H. Tenhunen, "Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era," in TVLSI, 2017. Google Scholar
Digital Library
- A. M. Rahmani, A. Jantsch, and N. Dutt, "HDGM: Hierarchical Dynamic Goal Management for Many-Core Resource Allocation," in ESL, 2017.Google Scholar
- P. J. Ramadge and W. M. Wonham, "The control of discrete event systems," in Proceedings of the IEEE, 1989. Google Scholar
Digital Library
- M. H. Safanov, Focusing on the knowable: Controller invalidation and learning. Springer, 1997.Google Scholar
- S. Skogestad and I. Postlethwaite, Multivariable Feedback Control: Analysis and Design. John Wiley&Sons, 2005. Google Scholar
Digital Library
- S. Srikantaiah, M. Kandemir, and Q. Wang, "SHARP control: Controlled shared cache management in chip multiprocessors," in MICRO, 2009. Google Scholar
Digital Library
- J. Stuecheli, D. Kaseridis, D. Daly, H. C. Hunter, and L. K. John, "The virtual write queue: Coordinating dram and last-level cache policies," in ISCA, 2010. Google Scholar
Digital Library
- B. Su, J. Gu, L. Shen, W. Huang, J. L. Greathouse, and Z. Wang, "PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration," in MICRO, 2014. Google Scholar
Digital Library
- L. Subramanian, V. Seshadri, Y. Kim, B. Jaiyen, and O.Mutlu, "Mise: Providing performance predictability and improving fairness in shared main memory systems," in HPCA, 2013. Google Scholar
Digital Library
- L. Subramanian, V. Seshadri, A. Ghosh, S. Khan, and O. Mutlu, "The Application Slowdown Model: Quantifying and Controlling the Impact of Inter-application Interference at Shared Caches and Main Memory," in MICRO, 2015. Google Scholar
Digital Library
- X. Sui, A. Lenharth, D. S. Fussell, and K. Pingali, "Proactive Control of Approximate Programs," in ASPLOS, 2016. Google Scholar
Digital Library
- P. Tembey, A. Gavrilovska, and K. Schwan, "A Case for Coordinated Resource Management in Heterogeneous Multicore Platforms," in ISCA, 2012. Google Scholar
Digital Library
- R. Teodorescu and J. Torrellas, "Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors," in ISCA, 2008. Google Scholar
Digital Library
- J. Thistle, "Supervisory control of discrete event systems," in Mathematical and Computer Modelling, 1996. Google Scholar
Digital Library
- V. Vardhan, W. Yuan, A. F. Harris, S. V. Adve, R. Kravets, K. Nahrstedt, D. Sachs, and D. Jones, "GRACE-2: integrating ine-grained application adaptation with global adaptation for saving energy," in IJES, 2009.Google Scholar
- A. Vega, A. Buyuktosunoglu, H. Hanson, P. Bose, and S. Ramani, "Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control," in ISCA, 2013. Google Scholar
Digital Library
- X. Wang and J. F. Martínez, "ReBudget: Trading Of Eiciency vs. Fairness in Market-Based Multicore Resource Allocation via Runtime Budget Reassignment," in ASPLOS, 2016. Google Scholar
Digital Library
- X. Wang, K. Ma, and Y. Wang, "Adaptive Power Control with Online Model Estimation for Chip Multiprocessors," in TPDS, 2011. Google Scholar
Digital Library
- Y.Wang, K. Ma, and X.Wang, "Temperature-constrained Power Control for Chip Multiprocessors with Online Model Estimation," in ISCA, 2009. Google Scholar
Digital Library
- Q. Wu, Q. Deng, L. Ganesh, C.-H. Hsu, Y. Jin, S. Kumar, B. Li, J. Meza, and Y. J. Song, "Dynamo: Facebook's Data Center-Wide Power Management System," in ISCA, 2016. Google Scholar
Digital Library
- Q. Wu, P. Juang, M. Martonosi, L.-S. Peh, and D. W. Clark, "Formal control techniques for power-performance management, 2005," in IEEE Micro, 2005. Google Scholar
Digital Library
- K. Yan, X. Zhang, J. Tan, and X. Fu, "Redeining QoS and customizing the power management policy to satisfy individual mobile users," in MICRO, 2016. Google Scholar
Digital Library
- H. Zhang and H. Hofmann, "Maximizing Performance Under a Power Cap: A Comparison of Hardware, Software, and Hybrid Techniques," in ASPLOS, 2016. Google Scholar
Digital Library
Index Terms
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management
Recommendations
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management
ASPLOS '18: Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating SystemsResource management strategies for many-core systems need to enable sharing of resources such as power, processing cores, and memory bandwidth while coordinating the priority and significance of system- and application-level objectives at runtime in a ...
SPECTR: Scalable Parallel Short Read Error Correction on Multi-core and Many-core Architectures
ICPP '18: Proceedings of the 47th International Conference on Parallel ProcessingModern high throughput sequencing platforms can produce large amounts of short read DNA data at low cost. Error correction is an important but time-consuming initial step when processing this data in order to improve the quality of downstream analyses. ...
HESSLE-FREE: Heterogeneous Systems Leveraging Fuzzy Control for Runtime Resource Management
Special Issue ESWEEK 2019, CASES 2019, CODES+ISSS 2019 and EMSOFT 2019As computing platforms increasingly embrace heterogeneity, runtime resource managers need to efficiently, dynamically, and robustly manage shared resources (e.g., cores, power budgets, memory bandwidth). To address the complexities in heterogeneous ...







Comments