research-article

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Nimble Page Management for Tiered Memory Systems

Authors:

David Nellans, and

Abhishek BhattacharjeeAuthors Info & Claims

ASPLOS '19: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems

April 2019

Pages 331 - 345

https://doi.org/10.1145/3297858.3304024

Published: 04 April 2019 Publication History

Abstract

Software-controlled heterogeneous memory systems have the potential to increase the performance and cost efficiency of computing systems. However they can only deliver on this promise if supported by efficient page management policies and mechanisms within the operating system (OS). Current OS implementations do not support efficient tiering of data between heterogeneous memories. Instead, they rely on expensive offlining of memory or swapping data to disk as a means of profiling and migrating hot or cold data between memory nodes. They also leave numerous optimizations on the table; for example, multi-threaded hardware is not leveraged to maximize page migration throughput, resulting in up to 95% under-utilization of available memory bandwidth. To remedy these shortcomings, we propose and implement a general purpose OS-integrated multi-level memory management system that reuses current OS page tracking structures to tier pages directly between memories with no additional monitoring overhead. We augment this system with four additional optimizations: native support for transparent huge page migration, multi-threaded migration of a page, concurrent migration of multiple pages, and symmetric exchange of pages. Combined, these optimizations dramatically reduce kernel software overheads and improve raw page migration throughput over 15×. Implemented in Linux and evaluated on x86, Power, and ARM64 systems, our OS support for heterogeneous memories improves application performance 40% over baseline Linux for a suite of real-world memory-intensive workloads utilizing a multi-level disaggregated memory system.

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Index Terms

Nimble Page Management for Tiered Memory Systems
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Virtual memory

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cover image ACM Conferences

ASPLOS '19: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems

April 2019

1126 pages

ISBN:9781450362405

DOI:10.1145/3297858

General Chairs:
Iris Bahar
Brown University
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Maurice Herlihy
Brown University
,
Program Chairs:
Emmett Witchel
University of Texas, Austin
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Alvin Lebeck
Duke University

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Xu CLiu YLi ZChen QZhao HZeng DPeng QWu XZhao HFu SGuo MTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)FaaSMem: Improving Memory Efficiency of Serverless Computing with Memory Pool ArchitectureProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3620666.3651355(331-348)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620666.3651355
Chang CHan JSivasubramaniam ASharma Mailthody VQureshi ZHwu WTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)GMT: GPU Orchestrated Memory Tiering for the Big Data EraProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3620666.3651353(464-478)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620666.3651353
Riekenbrauck NWeisgut MLindner DRabl T(2024)A Three-Tier Buffer Manager Integrating CXL Device Memory for Database Systems2024 IEEE 40th International Conference on Data Engineering Workshops (ICDEW)10.1109/ICDEW61823.2024.00063(395-401)Online publication date: 13-May-2024
https://doi.org/10.1109/ICDEW61823.2024.00063
Wang YLi BJaleel AYang JTang X(2024)GRIT: Enhancing Multi-GPU Performance with Fine-Grained Dynamic Page Placement2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00085(1080-1094)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00085
Hong JCho SPark GYang WGong YKim G(2024)Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00021(139-155)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00021
Sefati ADolati MGhaderi M(2023)Workload Placement with Bounded Slowdown in Disaggregated Datacenters2023 19th International Conference on Network and Service Management (CNSM)10.23919/CNSM59352.2023.10327871(1-9)Online publication date: 30-Oct-2023
https://doi.org/10.23919/CNSM59352.2023.10327871
SHU JCHEN YWANG QWANG JLI JLIAO X(2023)Progress on storage systems for disaggregated data centersSCIENTIA SINICA Informationis10.1360/SSI-2023-003453:8(1503)Online publication date: 17-Aug-2023
https://doi.org/10.1360/SSI-2023-0034
Ni YMehra PMiller ELitz H(2023)TMCProceedings of the 2023 ACM Symposium on Cloud Computing10.1145/3620678.3624667(376-393)Online publication date: 30-Oct-2023
https://dl.acm.org/doi/10.1145/3620678.3624667
Sun YYuan YYu ZKuper RSong CHuang JJi HAgarwal SLou JJeong IWang RAhn JXu TKim N(2023)Demystifying CXL Memory with Genuine CXL-Ready Systems and DevicesProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614256(105-121)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614256
Aguilera MAmaro EAmit NHunhoff EYelam AZellweger G(2023)Memory disaggregation: why now and what are the challengesACM SIGOPS Operating Systems Review10.1145/3606557.360656357:1(38-46)Online publication date: 28-Jun-2023
https://dl.acm.org/doi/10.1145/3606557.3606563
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