skip to main content
article
Public Access

Decoupling address generation from loads and stores to improve data access energy efficiency

Published:19 June 2018Publication History
Skip Abstract Section

Abstract

Level-one data cache (L1 DC) accesses impact energy usage as they frequently occur and use significantly more energy than register file accesses. A memory access instruction consists of an address generation operation calculating the location where the data item resides in memory and the data access operation that loads/stores a value from/to that location. We propose to decouple these two operations into separate machine instructions to reduce energy usage. By associating the data translation lookaside buffer (DTLB) access and level-one data cache (L1 DC) tag check with an address generation instruction, only a single data array in a set-associative L1 DC needs to be accessed during a load instruction when the result of the tag check is known at that point. In addition, many DTLB accesses and L1 DC tag checks are avoided by memoizing the DTLB way and L1 DC way with the register that holds the memory address to be dereferenced. Finally, we are able to often coalesce an ALU operation with a load or store data access using our technique to reduce the number of instructions executed.

References

  1. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors. Speculative tag access for reduced energy dissipation in set-associative l1 data caches. In Proceedings of the IEEE International Conference on Computer Design (ICCD 2013), Oct. 2013.Google ScholarGoogle ScholarCross RefCross Ref
  2. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors. Reducing set-associative l1 data cache energy by early load data dependence detection (eld3). In IEEE/ACM Design Automation and Test in Europe Conference, March 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors. Improving data access efficiency by using context-aware loads and stores. In ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. A. Basu, M. Hill, and M. Swift. Reducing memory reference energy with opportunistic virtual caching. In Proceedings of ACM/IEEE International Symposium on Computer Architecture, pages 297–308, June 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. M. E. Benitez and J. W. Davidson. A portable global optimizer and linker. In Proceedings of the SIGPLAN Symposium on Programming Language Design and Implementation, pages 329–338, June 1988. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In Proc. Int. Workshop on Workload Characterization, pages 3–14, Dec. 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. K. Inoue, T. Ishihara, and K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption. In Proc. IEEE Int. Symp. on Low Power Design (ISLPED), pages 273–275, Aug. 1999. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. Kin, M. Gupta, and W. Mangione-Smith. The filter cache: An energy efficient memory structure. In Proc. Int. Symp. on Microarchitecture, pages 184–193, Dec. 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. D. Moreau, A. Bardizbanyan, M. Själander, D. Whalley, and P. LarssonEdefors. Practical way halting by speculatively accessing halt tags. In Proceedings of the IEEE Design, Automation, and Test in Europe (DATE 2016), Mar. 2016. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. D. Nicolaescu, B. Salamat, A. Veidenbaum, and M. Valero. Fast speculative address generation and way caching for reducing l1 data cache energy. In Proceedings of International Conference on Computer Design, Oct. 2007.Google ScholarGoogle Scholar
  11. S. Önder and R. Gupta. Automatic generation of microarchitecture simulators. In IEEE International Conference on Computer Languages, pages 80–89, Chicago, May 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. M. D. Powell, A. Agarwal, T. N. Vijaykumar, B. Falsafi, and K. Roy. Reducing set-associative cache energy via way-prediction and selective direct-mapping. In Proc. ACM/IEEE Int. Symp. on Microarchitecture (MICRO), pages 54–65, Dec. 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. A. Sembrant, E. Hagersten, and D. Black-Shaffer. Tlc: A tag-less cache for reducing dynamic first level cache energy. In Proc. 46th ACM/IEEE Int. Symp. on Microarchitecture (MICRO), pages 351–356, Dec. 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. C. Su and A. Despain. Cache design trade-offs for power and performance optimization: A case study. In Proc. Int. Symp. on Low Power Design (ISLPED), pages 63–68, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. E. Witchel, S. Larsen, C. S. Ananian, and K. Asanović. Direct addressed caches for reduced power consumption. In Proc. 34th ACM/IEEE Int. Symp. on Microarchitecture (MICRO), pages 124–133, Dec. 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. C. Zhang, F. Vahid, J. Yang, and W. Najjar. A way-halting cache for lowenergy high-performance systems. ACM Transactions on Architecture and Compiler Optimizations (TACO), 2(1):34–54, Mar. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Z. Zheng, Z. Wang, and M. Lipasti. Tag check elision. In International Symposium on Low Power Electronics and Design, pages 351–356, New York, NY, USA, 2014. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Decoupling address generation from loads and stores to improve data access energy efficiency

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 53, Issue 6
        LCTES '18
        June 2018
        112 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/3299710
        Issue’s Table of Contents
        • cover image ACM Conferences
          LCTES 2018: Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems
          June 2018
          112 pages
          ISBN:9781450358033
          DOI:10.1145/3211332

        Copyright © 2018 ACM

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 19 June 2018

        Check for updates

        Qualifiers

        • article

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!