Abstract
The semiconductor design industry of the embedded era has embraced the globalization strategy for system on chip (SoC) design. This involves incorporation of various SoC components or intellectual properties (IPs), procured from various third-party IP (3PIP) vendors. However, trust of an SoC is challenged when a supplied IP is counterfeit or implanted with a Hardware Trojan Horse. Both roots of untrust may result in sudden performance degradation at runtime. None of the existing hardware security approaches organize the behavior of the IPs at the low level, to ensure timely completion of SoC operations. However, real-time SoC operations are always associated with a deadline, and a deadline miss due to sudden performance degradation of any of the IPs may jeopardize mission-critical applications. We seek refuge to the stigmergic behavior exhibited in insect colonies to propose a decentralized self-aware security approach. The self-aware security modules attached with each IP works based on the Observe-Decide-Act paradigm and not only detects vulnerability but also organizes behavior of the IPs dynamically at runtime so that the high-level objective of task completion before a deadline is ensured. Experimental validation and low overhead of our proposed security modules over various benchmark IPs and crypto SoCs depict the prospects of our proposed mechanism.
- H. A. M. Amin, Y. Alkabani, and G. M. I. Selim. 2014. System-level protection and hardware Trojan detection using weighted voting. Journal of Advanced Research 5, 4 (2014), 499--505.Google Scholar
Cross Ref
- S. Bhunia, M. S. Hsiao, M. Banga, and S. Narasimhan. 2014. Hardware Trojan attacks: Threat analysis and countermeasures. Proceedings of the IEEE 102, 8 (2014), 1229--1247.Google Scholar
Cross Ref
- Defense Science Board. 2005. Defense Science Board Task Force on High Performance Microchip Supply. Available at https://www.acq.osd.mil/dsb/reports/2000s/ada435563.pdf.Google Scholar
- D. Brelaz. 1979. New methods to color vertices of a graph. Communications of the ACM 22, 4 (1979), 251--256. Google Scholar
Digital Library
- S. Camazine, J. L. Deneubourg, N. R. Franks, J. Sneyd, G. Theraulaz, and E. Bonabeau. 2001. Self Organization in Biological Systems. Princeton University Press, Princeton, NJ. Google Scholar
Digital Library
- J. Cassell. 2012. Reports of Counterfeit Parts Quadruple Since 2009, Challenging US Defense Industry and National Security. IHS Markit. Retrieved February 11, 2019 from https://technology.ihs.com/389481/reports-of-counterfeit-parts-quadruple-since-2009-challenging-us-defense-industry-and-national-security.Google Scholar
- R. S. Chakraborty and S. Bhunia. 2009. HARPOON: An obfuscation-based SoC design methodology for hardware protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 10 (Oct. 2009), 1493--1502. Google Scholar
Digital Library
- R. S. Chakraborty and S. Bhunia. 2011. Security against hardware Trojan attacks using key-based design obfuscation. Journal of Electronic Testing 27, 6 (2011), 767--785.Google Scholar
Cross Ref
- R. S. Chakraborty, F. Wolff, S. Paul, C. Papachristou, and S. Bhunia. 2009. MERO: A statistical approach for hardware Trojan detection. In Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems (CHES’09). 396--410. Google Scholar
Digital Library
- K. Chatterjee and D. Das. 2007. Semiconductor manufacturers’ efforts to improve trust in the electronic part supply chain. IEEE Transactions on Components and Packaging Technologies 30, 3 (2007), 547--549.Google Scholar
Cross Ref
- A. Cornejo, A. Dornhaus, N. Lynch, and R. Nagpal. 2014. Task Allocation in Ant Colonies. Springer, Berlin, Germany, 46--60.Google Scholar
- X. Cui, K. Ma, L. Shi, and K. Wu. 2014. High-level synthesis for run-time hardware Trojan detection and recovery. In Proceedings of the 51st Annual Design Automation Conference (DAC’14). 157:1--157:6. Google Scholar
Digital Library
- X. Cui, K. Wu, T. Wei, and E. H. Sha. 2016. Worst-case finish time analysis for DAG-based applications in the presence of transient faults. Journal of Computer Science and Technology 31, 2 (2016), 267--283.Google Scholar
Cross Ref
- M. Dorigo, V. Maniezzo, and A. Colorni. 1996. Ant system: Optimization by a colony of cooperating agents. IEEE Transactions on Systems, Man, and Cybernetics, Part B 26, 1 (1996), 29--41. Google Scholar
Digital Library
- A. Dornhaus, J. A. Holley, V. G. Pook, G. Worswick, and N. R. Franks. 2008. Why do not all workers work? Colony size and workload during emigrations in the ant Temnothorax albipennis. Behavioral Ecology and Sociobiology 63, 1 (Nov. 2008), 43--51.Google Scholar
Cross Ref
- R. Falcon, M. Almeida, and A. Nayak. 2010. A binary particle swarm optimization approach to fault diagnosis in parallel and distributed systems. In Proceedings of the IEEE Congress on Evolutionary Computation. 1--8.Google Scholar
- S. Ghosh and D. R. Chowdhury. 2015. Preventing fault attack on stream cipher using randomization. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST’15). 88--91.Google Scholar
- K. Guha, D. Saha, and A. Chakrabarti. 2015. RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks. In Proceedings of the 2015 19th International Symposium on VLSI Design and Test. 1--6.Google Scholar
- K. Guha, D. Saha, and A. Chakrabarti. 2017a. Self aware SoC security to counteract delay inducing hardware trojans at runtime. In Proceedings of the 2017 30th International Conference on VLSI Design and the 2017 16th International Conference on Embedded Systems (VLSID’17). 417--422.Google Scholar
- K. Guha, D. Saha, and A. Chakrabarti. 2017b. Real-time SoC security against passive threats using crypsis behavior of Geckos. ACM Journal on Emerging Technologies in Computing Systems 13, 3, Article 41, 26 pages. Google Scholar
Digital Library
- U. Guin, D. DiMase, and M. Tehranipoor. 2014. Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead. Journal of Electronic Testing 30, 1 (Feb. 2014), 9--23. Google Scholar
Digital Library
- F. Heylighen. 2016. Stigmergy as a universal coordination Mechanism I. Elsevier Cognitive Systems Research 38, C (2016), 4--13. Google Scholar
Digital Library
- ITRS. 2013. International Technology Roadmap for Semiconductors Report. Retrieved February 11, 2019 from https://www.semiconductors.org/wp-content/uploads/2018/08/2013ExecutiveSummary.pdf.Google Scholar
- J. Keane, X. Wang, P. Jain, and C. H. Kim. 2014. On-chip silicon odometers for circuit aging characterization. In Bias Temperature Instability for Devices and Circuits. Springer, 679--717.Google Scholar
- J. Kennedy and R. Eberhart. 1995. Particle swarm optimization. In Proceedings of the IEEE International Conference on Neural Networks, Vol. 4. 1942--1948.Google Scholar
- T. H. Kim, R. Persaud, and C. H. Kim. 2008. Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits. IEEE Journal of Solid-State Circuits 43, 4 (2008), 874--880.Google Scholar
Cross Ref
- C. Liu, J. Rajendran, C. Yang, and R. Karri. 2013. Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. In Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS’13). 101--106.Google Scholar
- E. Love, Y. Jin, and Y. Makris. 2012. Proof-carrying hardware intellectual property: A pathway to trusted module acquisition. IEEE Transactions on Information Forensics and Security 7, 1 (2012), 25--40. Google Scholar
Digital Library
- D. McIntyre, F. Wolff, C. Papachristou, S. Bhunia, and D. Weyer. 2009. Dynamic evaluation of hardware trust. In Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust. 108--111. Google Scholar
Digital Library
- S. Narasimhan, D. Du, R. S. Chakraborty, S. Paul, F. G. Wolff, C. A. Papachristou, et al. 2013. Hardware Trojan detection by multiple-parameter side-channel analysis. IEEE Transactions on Computers 62, 11 (2013), 2183--2195. Google Scholar
Digital Library
- OpenCores Benchmarks. 2016. OpenCore Projects (Crypto Core Benchmarks). Retreived February 11, 2019 from https://opencores.org/projects.Google Scholar
- M. Pecht and S. Tiku. 2006. Bogus: Electronic manufacturing and consumers confront a rising tide of counterfeit electronics. IEEE Spectrum 43, 5 (2006), 37--46. Google Scholar
Digital Library
- J. Rajendran, H. Zhang, O. Sinanoglu, and R. Karri. 2013. High-level synthesis for security and trust. In Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS’13). 232--233.Google Scholar
- J. J. Rajendran, O. Sinanoglu, and R. Karri. 2016. Building trustworthy systems using untrusted components: A high-level synthesis approach. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, 9 (2016), 2946--2959.Google Scholar
Digital Library
- S. Sarma, N. Dutt, P. Gupta, N. Venkatasubramanian, and A. Nicolau. 2015. Cyberphysical-system-on-chip (CPSoC): A self-aware MPSoC paradigm with cross-layer virtual sensing and actuation. In Proceedings of the 2015 Design, Automation, and Test in Europe Conference and Exhibition (DATE’15). 625--628. Google Scholar
Digital Library
- A. Sengupta, S. Bhadauria, and S. P. Mohanty. 2017. TL-HLS: Methodology for low cost hardware Trojan security aware scheduling with optimal loop unrolling factor during high level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, 4 (2017), 655--668. Google Scholar
Digital Library
- H. G. Stratigopoulos, S. Mir, L. Abdallah, and J. Altet. 2013. Defect-oriented non-intrusive RF test using on-chip temperature sensors. In Proceedings of the 2013 IEEE 31st VLSI Test Symposium (VTS’13). 1--6. Google Scholar
Digital Library
- G. E. Suh and S. Devadas. 2007. Physical unclonable functions for device authentication and secret key generation. In Proceedings of the 44th Annual Design Automation Conference (DAC’07). 9--14. Google Scholar
Digital Library
- C. K. H. Suresh, S. Ozev, and O. Sinanoglu. 2015. Adaptive generation of unique IDs for digital chips through analog excitation. ACM Transactions on Design Automation of Electronic Systems 20, 3 (2015), Article 46. Google Scholar
Digital Library
- A. Teske, R. Falcon, and A. Nayak. 2015. Efficient detection of faulty nodes with Cuckoo search in T-diagnosable systems. Applied Soft Computing 29, C (2015), 52--64. Google Scholar
Digital Library
- G. Theraulaz and Bonabeau. 1998. Response threshold reinforcements and division of labour in insect societies. Proceedings of the Royal Society of London B: Biological Sciences 265, 1393 (1998), 327--332.Google Scholar
Cross Ref
- J. Werfel, K. Petersen, and R. Nagpal. 2014. Designing collective behavior in a termite inspired robot construction team. Science 343, 6172 (2014), 754--758.Google Scholar
- K. Xiao, X. Zhang, and M. Tehranipoor. 2013. A clock sweeping technique for detecting hardware Trojans impacting circuits delay. IEEE Design and Test 30, 2 (2013), 26--34.Google Scholar
Cross Ref
- Xilinx Inc. 2018. ZynQ-7000 SoC Technical Reference Manual UG585. Retrieved February 11, 2019 from https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf.Google Scholar
- X. S. Yang and S. Deb. 2009. Cuckoo search via levy flights. In Proceedings of the 2009 World Congress on Nature Biologically Inspired Computing (NaBIC’09). 210--214.Google Scholar
- X. Zhang, K. Xiao, and M. Tehranipoor. 2012. Path-delay fingerprinting for identification of recovered ICs. In Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 13--18. Google Scholar
Digital Library
- Y. Zheng, X. Wang, and S. Bhunia. 2015. SACCI: Scan-based characterization through clock phase sweep for counterfeit chip detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, 5 (2015), 831--841.Google Scholar
Digital Library
Index Terms
Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components
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