Abstract
The approaching end of DRAM scaling and expansion of emerging memory technologies is motivating a lot of research in future memory systems. Novel memory systems are typically explored by hardware simulators that are slow and often have a simplified or obsolete abstraction of the CPU. This study presents PROFET, an analytical model that predicts how an application's performance and energy consumption changes when it is executed on different memory systems. The model is based on instrumentation of an application execution on actual hardware, so it already takes into account CPU microarchitectural details such as the data prefetcher and out-of-order engine. PROFET is evaluated on two real platforms: Sandy Bridge-EP E5-2670 and Knights Landing Xeon Phi platforms with various memory configurations. The evaluation results show that PROFET's predictions are accurate, typically with only 2% difference from the values measured on actual hardware. We release the PROFET source code and all input data required for memory system and application profiling. The released package can be seamlessly installed and used on high-end Intel platforms.
- Arira Design. 2013. Hybrid Memory Cube Evaluation & Development Board. http://www.ariradesign.com/hmc-board.Google Scholar
- Yuan Chou, Brian Fahs, and Santosh Abraham. 2004. Microarchitecture Optimizations for Exploiting Memory-Level Parallelism. In Proceedings of the 31st Annual International Symposium on Computer Architecture. 76--87. Google Scholar
Digital Library
- R. Clapp, M. Dimitrov, K. Kumar, V. Viswanathan, and T. Willhalm. 2015. Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data Workloads. In IEEE International Symposium on Workload Characterization. 213--224. Google Scholar
Digital Library
- Yokogawa Test & Measurement Corporation. {n.d.}. WT230 Digital Power Meter. https://cdn.tmi.yokogawa.com/IM760401-01E.pdf.Google Scholar
- S. Van den Steen, S. Eyerman, S. De Pestel, M. Mechri, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout. 2016. Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Trans. Comput., Vol. 65, 12 (Dec 2016), 3537--3551. Google Scholar
Digital Library
- Qingyuan Deng, David Meisner, Luiz Ramos, Thomas F. Wenisch, and Ricardo Bianchini. 2011. MemScale: Active Low-power Modes for Main Memory. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems. 225--238. Google Scholar
Digital Library
- P. G. Emma. 1997. Understanding some simple processor-performance limits. IBM Journal of Research and Development, Vol. 41, 3 (May 1997), 215--232. Google Scholar
Digital Library
- Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, and James E. Smith. 2006. A Performance Counter Architecture for Computing Accurate CPI Components. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems. 175--184. Google Scholar
Digital Library
- Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, and James E. Smith. 2009. A Mechanistic Performance Model for Superscalar Out-of-order Processors. ACM Trans. Comput. Syst., Vol. 27, 2 (May 2009), 3:1--3:37. Google Scholar
Digital Library
- Xixhou Feng, Rong Ge, and K. W. Cameron. 2005. Power and energy profiling of scientific applications on distributed systems. In IEEE International Parallel and Distributed Processing Symposium. Google Scholar
Digital Library
- D. Genbrugge, S. Eyerman, and L. Eeckhout. 2010. Interval simulation: Raising the level of abstraction in architectural simulation. In The Sixteenth International Symposium on High-Performance Computer Architecture. 307--318.Google Scholar
- Andrew Glew. 1998. MLP yes! ILP no! International Conference on Architectural Support for Programming Languages and Operating Systems, Wild and Crazy Ideas Session (Oct. 1998).Google Scholar
- John L. Hennessy and David A. Patterson. 2017. Computer Architecture: A Quantitative Approach 6th ed.). Google Scholar
Digital Library
- Intel Corporation. 2012a. Intel® Xeon® Processor E5--1600/E5--2600/E5--4600 Product Families Datasheet - Volume One. Technical Report 326508.Google Scholar
- Intel Corporation. 2012b. Intel® Xeon® Processor E5--2600 Product Family Uncore Performance Monitoring Guide. Technical Report.Google Scholar
- Intel Corporation. 2016. Intel® 64 and IA-32 Architectures Optimization Reference Manual. Technical Report.Google Scholar
- Intel Corporation. 2017. Intel® Xeon Phi#8482; Processor Performance Monitoring Reference Manual - Volume 2: Events. Technical Report.Google Scholar
- Bruce Jacob, Spencer Ng, and David Wang. 2007. Memory Systems: Cache, DRAM, Disk. Google Scholar
Digital Library
- Bruce L. Jacob. 2009. The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It. Synthesis Lectures on Computer Architecture, Vol. 4, 1 (2009), 1--77. Google Scholar
Digital Library
- James Jeffers, James Reinders, and Avinash Sodani. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition 2nd ed.). Google Scholar
Digital Library
- Tejas S. Karkhanis and James E. Smith. 2004. A First-Order Superscalar Processor Model. In Proceedings of the Annual International Symposium on Computer Architecture. 338--349. Google Scholar
Digital Library
- Y. Kim, W. Yang, and O. Mutlu. 2016. Ramulator: A Fast and Extensible DRAM Simulator. IEEE Computer Architecture Letters, Vol. 15, 1 (Jan. 2016), 45--49. Google Scholar
Digital Library
- Peter Kogge, Keren Bergman, Shekhar Borkar, Dan Campbell, William Carlson, William Dally, Monty Denneau, Paul Franzon, William Harrod, Kerry Hill, Jon Hiller, Sherman Karp, Stephen Keckler, Dean Klein, Robert Lucas, Mark Richards, Al Scarpelli, Steven Scott, Allan Snavely, Thomas Sterling, R. Stanley Williams, and Katherine Yelick. 2008. ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems .Google Scholar
- David Kroft. 1981. Lockup-free Instruction Fetch/Prefetch Cache Organization. In Proceedings of the Annual Symposium on Computer Architecture. 81--87. Google Scholar
Digital Library
- Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi. 2009. McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 469--480. Google Scholar
Digital Library
- John D. McCalpin. 1991--2007. STREAM: Sustainable Memory Bandwidth in High Performance Computers. Technical Report. University of Virginia. http://www.cs.virginia.edu/stream/Google Scholar
- Micron Technology, Inc. 2007. Calculating Memory System Power for DDR3. Technical Report TN-41-01.Google Scholar
- Micron Technology, Inc. 2013. MT36JSF1G72PZ-1G6M1, 8GB (x72, ECC, DR) 240-Pin DDR3 RDIMM. http://www.micron.com/~/media/documents/products/data-sheet/modules/parity_rdimm/jsf36c1gx72pz.pdf.Google Scholar
- Partnership for Advanced Computing in Europe (PRACE). 2013. Unified European Applications Benchmark Suite. www.prace-ri.eu/ueabs/.Google Scholar
- Milan Radulovic, Rommel Sanchez Verdejo, Paul Carpenter, Petar Radojkoviç, Bruce Jacob, and Eduard Ayguadé. 2019. PROFET -- Analytical model that quantifies the impact of the main memory on application performance and system power and energy consumption. https://github.com/bsc-mem/PROFET.Google Scholar
- P. Rosenfeld, E. Cooper-Balis, and B. Jacob. 2011. DRAMSim2: A Cycle Accurate Memory System Simulator. IEEE Computer Architecture Letters, Vol. 10, 1 (Jan. 2011), 16--19. Google Scholar
Digital Library
- Daniel Sanchez and Christos Kozyrakis. 2013. ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-core Systems. In Proceedings of the 40th Annual International Symposium on Computer Architecture. 475--486.Google Scholar
Digital Library
- Rommel Sanchez Verdejo, Kazi Asifuzzaman, Milan Radulovic, Petar Radojkoviç, Eduard Ayguadé, and Bruce Jacob. 2018. Main Memory Latency Simulation: The Missing Link. In Proceedings of the International Symposium on Memory Systems. 1--9.Google Scholar
Digital Library
- Avinash Sodani. 2011. Race to Exascale: Opportunities and Challenges. Keynote Presentation at the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).Google Scholar
- A. Sodani, R. Gramunt, J. Corbal, H. S. Kim, K. Vinod, S. Chinthamani, S. Hutsell, R. Agarwal, and Y. C. Liu. 2016. Knights Landing: Second-Generation Intel Xeon Phi Product. IEEE Micro, Vol. 36, 2 (March 2016), 34--46. Google Scholar
Digital Library
- Standard Performance Evaluation Corporation. {n.d.}. SPEC CPU 2006. http://www.spec.org/cpu2006/.Google Scholar
- Rick Stevens, Andy White, Pete Beckman, Ray Bair-ANL, Jim Hack, Jeff Nichols, Al GeistORNL, Horst Simon, Kathy Yelick, John Shalf-LBNL, Steve Ashby, Moe Khaleel-PNNL, Michel McCoy, Mark Seager, Brent Gorda-LLNL, John Morrison, Cheryl Wampler-LANL, James Peery, Sudip Dosanjh, Jim Ang-SNL, Jim Davenport, Tom Schlagel, BNL, Fred Johnson, and Paul Messina. 2010. A Decadal DOE Plan for Providing Exascale Applications and Technologies for DOE Mission Needs. Presentation at Advanced Simulation and Computing Principal Investigators Meeting.Google Scholar
- J. Treibig, G. Hager, and G. Wellein. 2010. LIKWID: A Lightweight Performance-Oriented Tool Suite for x86 Multicore Environments. In International Conference on Parallel Processing Workshops. 207--216. Google Scholar
Digital Library
- R. S. Verdejo and P. Radojković. 2017. Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators. In 2017 International Conference on High Performance Computing Simulation (HPCS). 881--883.Google Scholar
- Wm. A. Wulf and Sally A. McKee. 1995. Hitting the Memory Wall: Implications of the Obvious. ACM SIGARCH Computer Architecture News, Vol. 23, 1 (March 1995), 20--24. Google Scholar
Digital Library
Index Terms
PROFET: Modeling System Performance and Energy Without Simulating the CPU
Recommendations
PROFET: Modeling System Performance and Energy Without Simulating the CPU
SIGMETRICS '19: Abstracts of the 2019 SIGMETRICS/Performance Joint International Conference on Measurement and Modeling of Computer SystemsApplication performance on novel memory systems is typically estimated using a hardware simulator. The simulation is, however, time consuming, which limits the number of design options that can be explored within a practical length of time. Also, ...
PROFET: Modeling System Performance and Energy Without Simulating the CPU
Application performance on novel memory systems is typically estimated using a hardware simulator. The simulation is, however, time consuming, which limits the number of design options that can be explored within a practical length of time. Also, ...
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
MICRO-50 '17: Proceedings of the 50th Annual IEEE/ACM International Symposium on MicroarchitectureMany important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that exploit fast bulk bitwise operations to accelerate databases (bitmap indices, BitWeaving) and web ...






Comments