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Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

Published:10 October 2019Publication History
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Abstract

Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of volatile memory (RAM). To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the formal persistency semantics of mainstream hardware is unexplored to date. To close this gap, we present a formal declarative framework for describing concurrency models in the NVM context, and then develop the PARMv8 persistency model as an instance of our framework, formalising the persistency semantics of the ARMv8 architecture for the first time. To facilitate correct persistent programming, we study transactions as a simple abstraction for concurrency and persistency control. We thus develop the PSER (persistent serialisability) persistency model, formalising transactional semantics in the NVM context for the first time, and demonstrate that PSER correctly compiles to PARMv8. This then enables programmers to write correct, concurrent and persistent programs, without having to understand the low-level architecture-specific persistency semantics of the underlying hardware.

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Presentation at OOPSLA '19

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          cover image Proceedings of the ACM on Programming Languages
          Proceedings of the ACM on Programming Languages  Volume 3, Issue OOPSLA
          October 2019
          2077 pages
          EISSN:2475-1421
          DOI:10.1145/3366395
          Issue’s Table of Contents

          Copyright © 2019 Owner/Author

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 10 October 2019
          Published in pacmpl Volume 3, Issue OOPSLA

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