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Centaur: A Novel Architecture for Reliable, Low-Wear, High-Density 3D NAND Storage

Published:12 June 2020Publication History
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Abstract

Due to the high density storage demand coming from applications from different domains, 3D NAND flash is becoming a promising candidate to replace 2D NAND flash as the dominant non-volatile memory. However, denser 3D NAND presents various performance and reliability issues, which can be addressed by the 3D NAND specific full-sequence program (FSP) operation. The FSP programs multiple pages simultaneously to mitigate the performance degradation caused by the long latency 3D NAND baseline program operations. However, the FSP-enabled 3D NAND-based SSDs introduce lifetime degradation due to the larger write granularities accessed by the FSP. To address the lifetime issue, in this paper, we propose and experimentally evaluate Centaur, a heterogeneous 2D/3D NAND heterogeneous SSD, as a solution. Centaur has three main components: a lifetime-aware inter-NAND request dispatcher, a lifetime-aware inter-NAND work stealer, and a data migration strategy from 2D NAND to 3D NAND. We used twelve SSD workloads to compare Centaur against a state-of-the-art 3D NAND-based SSD with the same capacity. Our experimental results indicate that the SSD lifetime and performance are improved by 3.7x and 1.11x, respectively, when using our 2D/3D heterogeneous SSD.

References

  1. 200. Samsung K9XXG08UXD datasheet. https://www.samsung.com/. (March 200).Google ScholarGoogle Scholar
  2. 2007. Micron MT29F8G08BAA datasheet. https://www.micron.com/products/nand-flash/. (Feb. 2007).Google ScholarGoogle Scholar
  3. 2014. ONFI 4.0 Specification. http://www.onfi.org/. (April 2014).Google ScholarGoogle Scholar
  4. 2016. Samsung 960 EVO SSD. http://www.samsung.com/semiconductor/minisite/ssd/product/consumer/960evo.html. (Sept. 2016).Google ScholarGoogle Scholar
  5. 2017. Crucial BX300 SSD. http://www.crucial.com/usa/en/storage-ssd-bx300. (Aug. 2017).Google ScholarGoogle Scholar
  6. 2017. Toshiba TR200 3D NAND SSD. https://www.ocz.com/us/ssd/tr200. (Aug. 2017).Google ScholarGoogle Scholar
  7. 2018. Bcache: Linux kernel block layer cache. https://bcache.evilpiepirate.org/. (March 2018).Google ScholarGoogle Scholar
  8. 2018. Berkeley DB. https://www.oracle.com/database/berkeley-db/db.html. (2018).Google ScholarGoogle Scholar
  9. 2018. btrfs file-system. https://btrfs.wiki.kernel.org/index.php/Main_Page. (2018).Google ScholarGoogle Scholar
  10. 2018. dm-cache: a Linux kernel's device mapper target that allows creation of hybrid volumes. https://en.wikipedia. org/wiki/Dm-cache. (Oct. 2018).Google ScholarGoogle Scholar
  11. 2018. ext4 file-system. https://en.wikipedia.org/wiki/Ext4. (2018).Google ScholarGoogle Scholar
  12. 2018. flashcache: a disk cache component for the Linux kernel. https://en.wikipedia.org/wiki/Flashcache. (Oct. 2018).Google ScholarGoogle Scholar
  13. 2020. Apple iPhone. https://www.apple.com/iphone/. (April 2020).Google ScholarGoogle Scholar
  14. Jacob Alter, Ji Xue, Alma Dimnaku, and Evgenia Smirni. 2019. SSD Failures in the Field: Symptoms, Causes, and Prediction Models (SC '19).Google ScholarGoogle Scholar
  15. Seiichi Aritome. 2015. NAND Flash Memory Technologies. John Wiley & Sons, Inc.Google ScholarGoogle Scholar
  16. Rodolfo Azevedo, John D. Davis, Karin St rauss, Parikshit Gopalan, Mark Manasse, and Sergey Yekhanin. 2013. Zombie Memory: Extending Memory Lifetime by Reviving Dead Blocks. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA).Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. A. Ban. 1995. Flash file system. https://www.google.com/patents/US5404485. (April 4 1995). US Patent 5,404,485.Google ScholarGoogle Scholar
  18. Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch. 2017. Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).Google ScholarGoogle Scholar
  19. Adrian M. Caulfield, Laura M. Grupp, and Steven Swanson. 2009. Gordon: Using Flash Memory to Build Fast, Powerefficient Clusters for Data-intensive Applications. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Adrian M. Caulfield and Steven Swanson. 2013. QuickSAN: A Storage Area Network for Fast, Distributed, Solid State Disks. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA).Google ScholarGoogle Scholar
  21. R. A. Cernea, L. Pham, F. Moogat, S. Chan, B. Le, Y. Li, S. Tsao, T. Y. Tseng, K. Nguyen, J. Li, J. Hu, J. H. Yuh, C. Hsu, F. Zhang, T. Kamei, H. Nasu, P. Kliza, K. Htoo, J. Lutze, Y. Dong, M. Higashitani, J. Yang, H. S. Lin, V. Sakhamuri, A. Li, F. Pan, S. Yadala, S. Taigor, K. Pradhan, J. Lan, J. Chan, T. Abe, Y. Fukuda, H. Mukai, K. Kawakami, C. Liang, T. Ip, S. F. Chang, J. Lakshmipathi, S. Huynh, D. Pantelakis, M. Mofidi, and K. Quader. 2009. A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. IEEE Journal of Solid-State Circuits.Google ScholarGoogle ScholarCross RefCross Ref
  22. L. P. Chang. 2010. A Hybrid Approach to NAND-Flash-Based Solid-State Disks. IEEE Trans. Comput.Google ScholarGoogle Scholar
  23. Y. H. Chang, J. W. Hsieh, and T. W. Kuo. 2010. Improving Flash Wear-Leveling by Proactively Moving Static Data. IEEE Trans. Comput.Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Chih-Ping Chen, H. T. Lue, Chih-Chang Hsieh, Kuo-Pin Chang, K. Y. Hsieh, and C. Y. Lu. 2010. Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash. In 2010 International Electron Devices Meeting.Google ScholarGoogle Scholar
  25. F. Chen, M. Yang, Y. Chang, and T. Kuo. 2015. PWL: A progressive wear leveling to minimize data migration overheads for NAND flash devices. In 2015 Design, Automation Test in Europe Conference Exhibition (DATE).Google ScholarGoogle Scholar
  26. C. Monzio Compagnoni, A. Goda, A. S. Spinelli, P. Feeley, A. L. Lacaita, and A. Visconti. 2017. Reviewing the Evolution of the NAND Flash Technology. Proc. IEEE.Google ScholarGoogle Scholar
  27. Cagdas Dirik and Bruce Jacob. 2009. The Performance of PC Solid-state Disks (SSDs) As a Function of Bandwidth, Concurrency, Device Architecture, and System Organization. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA).Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. 2009. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Xiao-Yu Hu, Evangelos Eleftheriou, Robert Haas, Ilias Iliadis, and Roman Pletka. 2009. Write Amplification Analysis in Flash-based Solid State Drives. In Proceedings of SYSTOR 2009.Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Yang Hu, Hong Jiang, Dan Feng, Lei Tian, Hao Luo, and Shuping Zhang. 2011. Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity. In Proceedings of the international conference on Supercomputing (SC). Proc. ACM Meas. Anal. Comput. Syst., Vol. 4, No. 2, Article 28. Publication date: June 2020. 28:24 Chun-Yi Liu et al.Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Jian Huang, Anirudh Badam, Moinuddin K. Qureshi, and Karsten Schwan. 2015. Unified Address Translation for Memory-mapped SSDs with FlashMap. In Proceedings of the 42Nd Annual International Symposium on Computer Architecture (ISCA).Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Jae-Woo Im, Woo-Pyo Jeong, Doo-Hyun Kim, Sang-Wan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, You-Se Kim, Hyun-Wook Park, and others. 2015. 7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. In 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers.Google ScholarGoogle ScholarCross RefCross Ref
  33. Manzur Gill Joe E. Brewer. 2007. NonVolatile Memory Technologies with Emphasis on Flash. John Wiley & Sons, Inc.Google ScholarGoogle Scholar
  34. Dawoon Jung, Jeong-UK Kang, Heeseung Jo, Jin-Soo Kim, and Joonwon Lee. 2010. Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme. ACM Transactions on Embedded Computing Systems.Google ScholarGoogle Scholar
  35. Myoungsoo Jung and Mahmut Kandemir. 2012. An Evaluation of Different Page Allocation Strategies on High-speed SSDs. In Proceedings of the 4th USENIX Conference on Hot Topics in Storage and File Systems (HotStorage).Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. D. Kang, W. Jeong, C. Kim, D. H. Kim, Y. S. Cho, K. T. Kang, J. Ryu, K. M. Kang, S. Lee, W. Kim, H. Lee, J. Yu, N. Choi, D. S. Jang, J. D. Ihm, D. Kim, Y. S. Min, M. S. Kim, A. S. Park, J. I. Son, I. M. Kim, P. Kwak, B. K. Jung, D. S. Lee, H. Kim, H. J. Yang, D. S. Byeon, K. T. Park, K. H. Kyung, and J. H. Choi. 2016. 7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers. In 2016 IEEE International Solid-State Circuits Conference (ISSCC).Google ScholarGoogle Scholar
  37. C. Kim, J. H. Cho, W. Jeong, I. h Park, H. W. Park, D. H. Kim, D. Kang, S. Lee, J. S. Lee, W. Kim, J. Park, Y. l Ahn, J. Lee, J. h Lee, S. Kim, H. J. Yoon, J. Yu, N. Choi, Y. Kwon, N. Kim, H. Jang, J. Park, S. Song, Y. Park, J. Bang, S. Hong, B. Jeong, H. J. Kim, C. Lee, Y. S. Min, I. Lee, I. M. Kim, S. H. Kim, D. Yoon, K. S. Kim, Y. Choi, M. Kim, H. Kim, P. Kwak, J. D. Ihm, D. S. Byeon, J. y Lee, K. T. Park, and K. h Kyung. 2017. 11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. In 2017 IEEE International Solid-State Circuits Conference (ISSCC).Google ScholarGoogle ScholarCross RefCross Ref
  38. Miryeong Kwon, Jie Zhang, Gyuyoung Park, Wonil Choi, David Donofrio, John Shalf, Mahmut Kandemir, and Myoungsoo Jung. 2017. TraceTracker: Hardware/Software Co-Evaluation for Large-Scale I/O Workload Reconstruction. In 2016 IEEE International Symposium on Workload Characterization (IISWC).Google ScholarGoogle Scholar
  39. Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, and Ha-Joo Song. 2007. A Log Bufferbased Flash Translation Layer Using Fully-associative Sector Translation. ACM Trans. Embed. Comput. Syst..Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Cheng Li, Philip Shilane, Fred Douglis, Hyong Shim, Stephen Smaldone, and Grant Wallace. 2014. Nitro: A Capacity- Optimized SSD Cache for Primary Storage. In 2014 USENIX Annual Technical Conference (USENIX ATC 14).Google ScholarGoogle Scholar
  41. J. Li, X. Xu, X. Peng, and J. Liao. 2019. Pattern-based Write Scheduling and Read Balance-oriented Wear-Leveling for Solid State Drivers. In 2019 35th Symposium on Mass Storage Systems and Technologies (MSST).Google ScholarGoogle Scholar
  42. Yongkun Li, Patrick P.C. Lee, and John C.S. Lui. 2013. Stochastic Modeling of Large-scale Solid-state Storage Systems: Analysis, Design Tradeoffs and Optimization. In Proceedings of the ACM SIGMETRICS/International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS).Google ScholarGoogle Scholar
  43. Chunyi Liu, Jagadish Kotra, Myoungsoo Jung, and Mahmut Kandemir. 2018. PEN: Design and Evaluation of Partial- Erase for 3D NAND-Based High Density SSDs. In 16th USENIX Conference on File and Storage Technologies (FAST 18).Google ScholarGoogle Scholar
  44. Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu. 2018. HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).Google ScholarGoogle Scholar
  45. Rino Micheloni, Luca Crippa, and Roberto Ravasio. 2007. Double page programming system and method. https: //www.google.tl/patents/US20070030732. (Feb. 8 2007). US Patent 20070030732.Google ScholarGoogle Scholar
  46. M. Murugan and D. H. C. Du. 2011. Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead. In 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST).Google ScholarGoogle ScholarDigital LibraryDigital Library
  47. K. Park, O. Kwon, S. Yoon, M. Choi, I. Kim, B. Kim, M. Kim, Y. Choi, S. Shin, Y. Song, J. Park, J. Lee, C. Eun, H. Lee, H. Kim, J. Lee, J. Kim, T. Kweon, H. Yoon, T. Kim, D. Shim, J. Sel, J. Shin, P. Kwak, J. Han, K. Kim, S. Lee, Y. Lim, and T. Jung. 2011. A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology. In 2011 IEEE International Solid-State Circuits Conference (ISSCC).Google ScholarGoogle Scholar
  48. Alessia Marelli Rino Micheloni, Luca Crippa. 2010. Inside NAND Flash Memory. Springer Netherlands.Google ScholarGoogle Scholar
  49. Bianca Schroeder, Raghav Lagisetty, and Arif Merchant. 2016. Flash Reliability in Production: The Expected and the Unexpected. In 14th USENIX Conference on File and Storage Technologies (FAST 16).Google ScholarGoogle ScholarDigital LibraryDigital Library
  50. N. Shibata, K. Kanda, T. Shimizu, J. Nakai, O. Nagao, N. Kobayashi, M. Miakashi, Y. Nagadomi, T. Nakano, T. Kawabe, T. Shibuya, M. Sako, K. Yanagidaira, T. Hashimoto, H. Date, M. Sato, T. Nakagawa, H. Takamoto, J. Musha, T. Minamoto, M. Uda, D. Nakamura, K. Sakurai, T. Yamashita, J. Zhou, R. Tachibana, T. Takagiwa, T. Sugimoto, M. Ogawa, Y. Ochi, K. Kawaguchi, M. Kojima, T. Ogawa, T. Hashiguchi, R. Fukuda, M. Masuda, K. Kawakami, T. Someya, Y. Kajitani, Y. Matsumoto, N. Morozumi, J. Sato, N. Raghunathan, Y. L. Koh, S. Chen, J. Lee, H. Nasu, H. Sugawara, K. Hosono, T. Hisada, T. Kaneko, and H. Nakamura. 2019. 13.1 A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. In 2019 IEEE International Solid- State Circuits Conference - (ISSCC). Proc. ACM Meas. Anal. Comput. Syst., Vol. 4, No. 2, Article 28. Publication date: June 2020. Centaur: A Novel Architecture for Reliable, Low-Wear, High-Density 3D NAND Storage 28:25Google ScholarGoogle Scholar
  51. K. S. Shim, E. S. Choi, S. W. Jung, S. H. Kim, H. S. Yoo, K. S. Jeon, H. S. Joo, J. S. Oh, Y. S. Jang, K. J. Park, S. M. Choi, S. B. Lee, J. D. Koh, K. H. Lee, J. Y. Lee, S. H. Oh, S. H. Pyi, G. S. Cho, S. K. Park, J. W. Kim, S. K. Lee, and S. J. Hong. 2012. Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell. In 2012 4th IEEE International Memory Workshop.Google ScholarGoogle Scholar
  52. Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, and others. 2016. 7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. In 2016 IEEE International Solid-State Circuits Conference (ISSCC).Google ScholarGoogle ScholarCross RefCross Ref
  53. Arash Tavakkol, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2014. Unleashing the Potentials of Dynamism for Page Allocation Strategies in SSDs. In The 2014 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS).Google ScholarGoogle Scholar
  54. Arash Tavakkol, Pooyan Mehrvarzy, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2016. Performance Evaluation of Dynamic Page Allocation Strategies in SSDs. ACM Transactions on Modeling and Performance Evaluation of Computing Systems.Google ScholarGoogle Scholar
  55. Benny Van Houdt. 2013. A Mean Field Model for a Class of Garbage Collection Algorithms in Flash-based Solid State Drives. In Proceedings of the ACM SIGMETRICS/International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS).Google ScholarGoogle ScholarDigital LibraryDigital Library
  56. R. Yamashita, S. Magia, T. Higuchi, K. Yoneya, T. Yamamura, H. Mizukoshi, S. Zaitsu, M. Yamashita, S. Toyama, N. Kamae, J. Lee, S. Chen, J. Tao, W. Mak, X. Zhang, Y. Yu, Y. Utsunomiya, Y. Kato, M. Sakai, M. Matsumoto, H. Chibvongodze, N. Ookuma, H. Yabe, S. Taigor, R. Samineni, T. Kodama, Y. Kamata, Y. Namai, J. Huynh, S. E. Wang, Y. He, T. Pham, V. Saraf, A. Petkar, M. Watanabe, K. Hayashi, P. Swarnkar, H. Miwa, A. Pradhan, S. Dey, D. Dwibedy, T. Xavier, M. Balaga, S. Agarwal, S. Kulkarni, Z. Papasaheb, S. Deora, P. Hong, M. Wei, G. Balakrishnan, T. Ariki, K. Verma, C. Siau, Y. Dong, C. H. Lu, T. Miwa, and F. Moogat. 2017. 11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. In 2017 IEEE International Solid-State Circuits Conference (ISSCC).Google ScholarGoogle Scholar
  57. M. C. Yang, Y. M. Chang, C. W. Tsao, P. C. Huang, Y. H. Chang, and T. W. Kuo. 2014. Garbage collection and wear leveling for flash memory: Past and future. In 2014 International Conference on Smart Computing (SMARTCOMP).Google ScholarGoogle Scholar
  58. Q. Yang and J. Ren. 2011. I-CASH: Intelligently Coupled Array of SSD and HDD. In 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA).Google ScholarGoogle Scholar

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