skip to main content
research-article

Applying Multiple Level Cell to Non-volatile FPGAs

Authors Info & Claims
Published:12 July 2020Publication History
Skip Abstract Section

Abstract

Static random access memory– (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLCs) has not been fully exploited yet.

In this article, we study architecture of MLC-based NVFPGAs, and propose five cluster structures. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Based on explorations of the characteristics of MLC-based NVFPGAs, we further present MLC-aware timing-driven packing method to improve delay. In critical paths, our proposed method reduces the overhead of the additional delay in slow MLC cells. Experiments show that, compared to SRAM-based FPGAs, the proposed architecture with the proposed CAD flow can reduce the area, critical path delay and leakage power by 31%, 10%, and 95%, respectively.

References

  1. Vaughn Betz and Jonathan Rose. 1997. Cluster-based logic blocks for FPGAs: Area-efficiency vs. input sharing and size. In Proceedings of the Custom Integrated Circuits Conference (CICC’97). IEEE, 551--554.Google ScholarGoogle ScholarCross RefCross Ref
  2. Xunchao Chen, Navid Khoshavi, Jian Zhou, Dan Huang, Ronald F. DeMara, Jun Wang, Wujie Wen, and Yiran Chen. 2016. AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache. In Proceedings of the 53rd Annual Design Automation Conference. ACM, 170.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Yibo Chen, Jishen Zhao, and Yuan Xie. 2010. 3d-nonfar: Three-dimensional non-volatile FPGA architecture using phase change memory. In Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED’10). IEEE, 55--60.Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Charles Chiasson and Vaughn Betz. 2013. COFFE: Fully-automated transistor sizing for FPGAs. In Proceedings of the 2013 International Conference on Field-Programmable Technology (FPT’13). IEEE, 34--41.Google ScholarGoogle ScholarCross RefCross Ref
  5. Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, and Giovanni De Micheli. 2012. GMS: Generic memristive structure for non-volatile FPGAs. In Proceedings of the International Conference on VLSI and System-on-Chip (VLSI-SoC’12). IEEE, 94--98.Google ScholarGoogle Scholar
  6. Shuo Huai, Weining Song, Mengying Zhao, Xiaojun Cai, and Zhiping Jia. 2019. Performance-aware wear leveling for block RAM in nonvolatile FPGAs. In Proceedings of the 56th Annual Design Automation Conference 2019. ACM, 157.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Kejie Huang, Yajun Ha, Rong Zhao, Akash Kumar, and Yong Lian. 2014. A low active leakage and high reliability phase change memory (PCM) based non-volatile FPGA storage element. IEEE Trans. Circ. Syst. I: Regul. Pap. 61, 9 (2014), 2605--2613.Google ScholarGoogle ScholarCross RefCross Ref
  8. Kejie Huang, Rong Zhao, Wei He, and Yong Lian. 2015. High-density and high-reliability nonvolatile field-programmable gate array with stacked 1D2R RRAM array. IEEE Trans. VLSI Syst. 24, 1 (2015), 139--150.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, and Lesley Shannon. 2010. Odin ii-an open-source verilog hdl synthesis tool for cad research. In Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’10). IEEE, 149--156.Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Lei Jiang, Bo Zhao, Youtao Zhang, and Jun Yang. 2012. Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors. In Proceedings of the 49th Annual Design Automation Conference. ACM, 907--912.Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Christoforos Kachris and Dimitrios Soudris. 2016. A survey on reconfigurable accelerators for cloud computing. In Proceedings of the 26th International Conference on Field Programmable Logic and Applications (FPL’16). IEEE, 1--10.Google ScholarGoogle ScholarCross RefCross Ref
  12. Behnam Khaleghi and Hossein Asadi. 2018. A resistive RAM-based FPGA architecture equipped with efficient programming circuitry. IEEE Trans. Circ. Syst. I: Regul. Pap. 65, 7 (2018), 2196--2209.Google ScholarGoogle ScholarCross RefCross Ref
  13. Mark H. Kryder and Chang Soo Kim. 2009. After hard drives What comes next? IEEE Transactions on Magnetics 45, 10 (2009), 3406--3413.Google ScholarGoogle ScholarCross RefCross Ref
  14. Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, and Yuan Xie. 2017. Building energy-efficient multi-level cell STT-RAM caches with data compression. In Proceedings of the 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC’17). IEEE, 751--756.Google ScholarGoogle ScholarCross RefCross Ref
  15. Jason Luu, Jeff Goeders, Tim Liu, Alexander Marquardt, Ian Kuon, Jason Anderson, Jonathan Rose, and Vaughn Betz. 2013. VPR User’s Manual (Version 7.0).Google ScholarGoogle Scholar
  16. Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, et al. 2014. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Trans. Reconfig. Technol. Syst. 7, 2 (2014), 6.Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Jason Luu, Jonathan Rose, and Jason Anderson. 2014. Towards interconnect-adaptive packing for FPGAs. In Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays. ACM, 21--30.Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Alexander Marquardt, Vaughn Betz, and Jonathan Rose. 1999. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’99), Vol. 99. 37--46.Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Somnath Paul, Saibal Mukhopadhyay, and Swarup Bhunia. 2008. Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design 2008 (ICCAD’08). IEEE, 589--592.Google ScholarGoogle ScholarCross RefCross Ref
  20. Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, and Jason Anderson. 2012. The VTR project: Architecture and CAD for FPGAs from verilog to routing. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM, 77--86.Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Luca Sterpone and Massimo Violante. 2006. A new reliability-oriented place and route algorithm for SRAM-based FPGAs. IEEE Trans. Comput. 55, 6 (2006), 732--744.Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, et al. 2013. Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electr. Express 10, 23 (2013), 20130772--20130772.Google ScholarGoogle ScholarCross RefCross Ref
  23. Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, et al. 2015. Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. In Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits’15). IEEE, C172--C173.Google ScholarGoogle ScholarCross RefCross Ref
  24. Stephen M. Trimberger. 2015. Three ages of FPGAs: A retrospective on the first thirty years of FPGA technology. Proc. IEEE 103, 3 (2015), 318--331.Google ScholarGoogle Scholar
  25. UG440. 2018. Xilinx power estimator user guide.Google ScholarGoogle Scholar
  26. Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Li. 2014. Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. In Proceedings of the 32nd IEEE International Conference on Computer Design (ICCD’14). IEEE, 133--138.Google ScholarGoogle ScholarCross RefCross Ref
  27. Yuan Xue, Patrick Cronin, Chengmo Yang, and Jingtong Hu. 2015. Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’15). IEEE, 1--8.Google ScholarGoogle ScholarCross RefCross Ref
  28. Yuan Xue, Patrick Cronin, Chengmo Yang, and Jingtong Hu. 2016. Routing path reuse maximization for efficient NV-FPGA reconfiguration. In Proceedings of the 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC’16). IEEE, 360--365.Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Hengyu Zhao, Linuo Xue, Ping Chi, and Jishen Zhao. 2017. Approximate image storage with multi-level cell STT-MRAM main memory. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’17). IEEE, 268--275.Google ScholarGoogle ScholarCross RefCross Ref
  30. Weisheng Zhao, Eric Belhaire, Claude Chappert, and Pascale Mazoyer. 2009. Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit. ACM Trans. Embed. Comput. Syst. 9, 2 (2009), 14.Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Weisheng Zhao, Eric Belhaire, Virgile Javerliac, Claude Chappert, and Bernard Dieny. 2006. Evaluation of a non-volatile FPGA based on MRAM technology. In Proceedings of the IEEE International Conference on IC Design and Technology. 1--4.Google ScholarGoogle Scholar

Index Terms

  1. Applying Multiple Level Cell to Non-volatile FPGAs

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      HTML Format

      View this article in HTML Format .

      View HTML Format
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!