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Taming x86-TSO persistency

Published:04 January 2021Publication History
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Abstract

We study the formal semantics of non-volatile memory in the x86-TSO architecture. We show that while the explicit persist operations in the recent model of Raad et al. from POPL'20 only enforce order between writes to the non-volatile memory, it is equivalent, in terms of reachable states, to a model whose explicit persist operations mandate that prior writes are actually written to the non-volatile memory. The latter provides a novel model that is much closer to common developers' understanding of persistency semantics. We further introduce a simpler and stronger sequentially consistent persistency model, develop a sound mapping from this model to x86, and establish a data-race-freedom guarantee providing programmers with a safe programming discipline. Our operational models are accompanied with equivalent declarative formulations, which facilitate our formal arguments, and may prove useful for program verification under x86 persistency.

References

  1. Parosh Aziz Abdulla, Mohamed Faouzi Atig, Ahmed Bouajjani, K. Narayan Kumar, and Prakash Saivasan. 2021. Deciding Reachability under Persistent x86-TSO. Proc. ACM Program. Lang. 5, POPL, Article 56 ( Jan. 2021 ), 32 pages. https: //doi.org/10.1145/3434337 Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Parosh Aziz Abdulla, Mohamed Faouzi Atig, Bengt Jonsson, and Tuan Phong Ngo. 2018. Optimal Stateless Model Checking under the Release-Acquire Semantics. Proc. ACM Program. Lang. 2, OOPSLA, Article 135 (Oct. 2018 ), 29 pages. https: //doi.org/10.1145/3276505 Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Jade Alglave, Luc Maranget, and Michael Tautschnig. 2014. Herding Cats: Modelling, Simulation, Testing, and Data Mining for Weak Memory. ACM Trans. Program. Lang. Syst. 36, 2, Article 7 ( July 2014 ), 74 pages. https://doi.org/10.1145/2627752 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Joy Arulraj, Justin Levandoski, Umar Farooq Minhas, and Per-Ake Larson. 2018. Bztree: A High-Performance Latch-Free Range Index for Non-Volatile Memory. Proc. VLDB Endow. 11, 5 (Jan. 2018 ), 553-565. https://doi.org/10.1145/3164135. 3164147 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Mohamed Faouzi Atig, Ahmed Bouajjani, Sebastian Burckhardt, and Madanlal Musuvathi. 2010. On the Verification Problem for Weak Memory Models. In POPL. ACM, New York, NY, USA, 7-18. https://doi.org/10.1145/1706299.1706303 Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Kumud Bhandari, Dhruva R. Chakrabarti, and Hans-Juergen Boehm. 2012. Implications of CPU Caching on Byte-addressable Non-Volatile Memory Programming. Technical Report HPL-2012-236. Hewlett-Packard.Google ScholarGoogle Scholar
  7. Shimin Chen and Qin Jin. 2015. Persistent B+-Trees in Non-Volatile Main Memory. Proc. VLDB Endow. 8, 7 (Feb. 2015 ), 786-797. https://doi.org/10.14778/2752939.2752947 Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Jeremy Condit, Edmund B. Nightingale, Christopher Frost, Engin Ipek, Benjamin Lee, Doug Burger, and Derrick Coetzee. 2009. Better I/O Through Byte-addressable, Persistent Memory. In SOSP. ACM, New York, NY, USA, 133-146. https: //doi.org/10.1145/1629575.1629589 Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Tudor David, Aleksandar Dragojević, Rachid Guerraoui, and Igor Zablotchi. 2018. Log-Free Concurrent Data Structures. In USENIX ATC. USENIX Association, USA, 373-385.Google ScholarGoogle Scholar
  10. Michal Friedman, Naama Ben-David, Yuanhao Wei, Guy E. Blelloch, and Erez Petrank. 2020. NVTraverse: In NVRAM Data Structures, the Destination is More Important than the Journey. In PLDI. ACM, New York, NY, USA, 377-392. https://doi.org/10.1145/3385412.3386031 Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Michal Friedman, Maurice Herlihy, Virendra Marathe, and Erez Petrank. 2018. A Persistent Lock-free Queue for Non-volatile Memory. In PPoPP. ACM, New York, NY, USA, 28-40. https://doi.org/10.1145/3178487.3178490 Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Vaibhav Gogte, Stephan Diestelhorst, William Wang, Satish Narayanasamy, Peter M. Chen, and Thomas F. Wenisch. 2018. Persistency for Synchronization-free Regions. In PLDI. ACM, New York, NY, USA, 46-61. https://doi.org/10.1145/3192366. 3192367 Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Intel. 2015. Persistent Memory Programming. http://pmem.io/Google ScholarGoogle Scholar
  14. Intel. 2019. Intel 64 and IA-32 Architectures Software Developer's Manual (Combined Volumes). https://software.intel.com/ sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Order Number: 325462-069US.Google ScholarGoogle Scholar
  15. Joseph Izraelevitz, Hammurabi Mendes, and Michael L. Scott. 2016a. Brief Announcement: Preserving Happens-before in Persistent Memory. In SPAA. ACM, New York, NY, USA, 157-159. https://doi.org/10.1145/2935764.2935810 Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Joseph Izraelevitz, Hammurabi Mendes, and Michael L. Scott. 2016b. Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model. In DISC. Springer Berlin Heidelberg, Berlin, Heidelberg, 313-327.Google ScholarGoogle Scholar
  17. Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, and Stratis Viglas. 2015. Eficient Persist Barriers for Multicores. In MICRO. ACM, New York, NY, USA, 660-671. https://doi.org/10.1145/2830772.2830805 Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Artem Khyzha and Ori Lahav. 2020. Taming x86-TSO Persistency (Extended Version). https://arxiv.org/abs/ 2010.13593Google ScholarGoogle Scholar
  19. Michalis Kokologiannakis, Ori Lahav, Konstantinos Sagonas, and Viktor Vafeiadis. 2017. Efective Stateless Model Checking for C/C++ Concurrency. Proc. ACM Program. Lang. 2, POPL, Article 17 ( Dec. 2017 ), 32 pages. https://doi.org/10.1145/ 3158105 Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Aasheesh Kolli, Vaibhav Gogte, Ali Saidi, Stephan Diestelhorst, Peter M. Chen, Satish Narayanasamy, and Thomas F. Wenisch. 2017. Language-level Persistency. In ISCA. ACM, New York, NY, USA, 481-493. https://doi.org/10.1145/3079856.3080229 Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Aasheesh Kolli, Jef Rosen, Stephan Diestelhorst, Ali Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, and Thomas F. Wenisch. 2016. Delegated Persist Ordering. In MICRO. IEEE Press, Piscataway, NJ, USA, Article 58, 13 pages. http://dl.acm.org/citation.cfm?id= 3195638. 3195709Google ScholarGoogle Scholar
  22. Dexter Kozen. 1977. Lower bounds for natural proof systems. In SFCS. IEEE Computer Society, Washington, 254-266. https://doi.org/10.1109/SFCS. 1977.16 Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Ori Lahav, Nick Giannarakis, and Viktor Vafeiadis. 2016. Taming Release-Acquire Consistency. In POPL. ACM, New York, NY, USA, 649-662. https://doi.org/10.1145/2837614.2837643 Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Lucas Lersch, Xiangpeng Hao, Ismail Oukid, Tianzheng Wang, and Thomas Willhalm. 2019. Evaluating Persistent Memory Range Indexes. Proc. VLDB Endow. 13, 4 (Dec. 2019 ), 574-587. https://doi.org/10.14778/3372716.3372728 Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Jihang Liu, Shimin Chen, and Lujun Wang. 2020. LB+Trees: Optimizing Persistent Index Performance on 3DXPoint Memory. Proc. VLDB Endow. 13, 7 (March 2020 ), 1078-1090. https://doi.org/10.14778/3384345.3384355 Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Lun Liu, Todd Millstein, and Madanlal Musuvathi. 2017. A Volatile-by-Default JVM for Server Applications. Proc. ACM Program. Lang. 1, OOPSLA, Article 49 (Oct. 2017 ), 25 pages. https://doi.org/10.1145/3133873 Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Mapping 2019. C/C++11 mappings to processors. Retrieved July 3, 2019 from http://www.cl.cam.ac.uk/~pes20/cpp/ cpp0xmappings.htmlGoogle ScholarGoogle Scholar
  28. Daniel Marino, Abhayendra Singh, Todd Millstein, Madanlal Musuvathi, and Satish Narayanasamy. 2011. A Case for an SC-Preserving Compiler. In PLDI. ACM, New York, NY, USA, 199-210. https://doi.org/10.1145/1993498.1993522 Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Adam Morrison and Yehuda Afek. 2013. Fast Concurrent Queues for X86 Processors. In PPoPP. ACM, New York, NY, USA, 103-112. https://doi.org/10.1145/2442516.2442527 Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Ismail Oukid, Johan Lasperas, Anisoara Nica, Thomas Willhalm, and Wolfgang Lehner. 2016. FPTree: A Hybrid SCMDRAM Persistent and Concurrent B-Tree for Storage Class Memory. In SIGMOD. ACM, New York, NY, USA, 371-386. https://doi.org/10.1145/2882903.2915251 Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Scott Owens. 2010. Reasoning About the Implementation of Concurrency Abstractions on x86-TSO. In ECOOP. SpringerVerlag, Berlin, Heidelberg, 478-503. http://dl.acm.org/citation.cfm?id= 1883978. 1884011Google ScholarGoogle Scholar
  32. Scott Owens, Susmit Sarkar, and Peter Sewell. 2009. A Better x86 Memory Model: x86-TSO. In TPHOLs. Springer, Heidelberg, 391-407. https://doi.org/10.1007/978-3-642-03359-9_27 Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Steven Pelley, Peter M. Chen, and Thomas F. Wenisch. 2014. Memory Persistency. In ISCA. IEEE Press, Piscataway, NJ, USA, 265-276. http://dl.acm.org/citation.cfm?id= 2665671. 2665712Google ScholarGoogle Scholar
  34. Anton Podkopaev, Ori Lahav, and Viktor Vafeiadis. 2019. Bridging the Gap Between Programming Languages and Hardware Weak Memory Models. Proc. ACM Program. Lang. 3, POPL, Article 69 ( Jan. 2019 ), 31 pages. https://doi.org/10.1145/3290382 Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Azalea Raad and Viktor Vafeiadis. 2018. Persistence Semantics for Weak Memory: Integrating Epoch Persistency with the TSO Memory Model. Proc. ACM Program. Lang. 2, OOPSLA, Article 137 (Oct. 2018 ), 27 pages. https://doi.org/10.1145/3276507 Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Azalea Raad, John Wickerson, Gil Neiger, and Viktor Vafeiadis. 2020. Persistency Semantics of the Intel-x86 Architecture. Proc. ACM Program. Lang. 4, POPL, Article 11 ( Jan. 2020 ), 31 pages. https://doi.org/10.1145/3371079 Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Azalea Raad, John Wickerson, and Viktor Vafeiadis. 2019. Weak Persistency Semantics from the Ground Up: Formalising the Persistency Semantics of ARMv8 and Transactional Models. Proc. ACM Program. Lang. 3, OOPSLA, Article 135 (Oct. 2019 ), 27 pages. https://doi.org/10.1145/3360561 Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. Andy M. Rudof. 2019. Deprecating the PCOMMIT Instruction. https://software.intel.com/content/www/us/en/develop/ blogs/deprecate-pcommit-instruction.htmlGoogle ScholarGoogle Scholar
  39. Susmit Sarkar, Kayvan Memarian, Scott Owens, Mark Batty, Peter Sewell, Luc Maranget, Jade Alglave, and Derek Williams. 2012. Synchronising C/C+ + and POWER. In PLDI. ACM, New York, NY, USA, 311-322. https://doi.org/10.1145/2254064. 2254102 Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Steve Scargall. 2020. Programming Persistent Memory: A Comprehensive Guide for Developers. Apress Media, LLC. https: //doi.org/10.1007/978-1-4842-4932-1 Google ScholarGoogle ScholarCross RefCross Ref
  41. Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd Millstein, and Madanlal Musuvathi. 2012. End-to-End Sequential Consistency. SIGARCH Comput. Archit. News 40, 3 ( June 2012 ), 524-535. https://doi.org/10.1145/2366231. 2337220 Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. Viktor Vafeiadis, Thibaut Balabonski, Soham Chakraborty, Robin Morisset, and Francesco Zappa Nardelli. 2015. Common Compiler Optimisations are Invalid in the C11 Memory Model and what we can do about it. In POPL. ACM, New York, NY, USA, 209-220. https://doi.org/10.1145/2676726.2676995 Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Shivaram Venkataraman, Niraj Tolia, Parthasarathy Ranganathan, and Roy H. Campbell. 2011. Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory. In FAST. USENIX Association, USA, 5.Google ScholarGoogle Scholar
  44. Tianzheng Wang, Justin J. Levandoski, and Per-Åke Larson. 2018. Easy Lock-Free Indexing in Non-Volatile Memory. In ICDE. IEEE Computer Society, Los Alamitos, CA, USA, 461-472. https://doi.org/10.1109/ICDE. 2018.00049 Google ScholarGoogle ScholarCross RefCross Ref
  45. John Wickerson, Mark Batty, Tyler Sorensen, and George A. Constantinides. 2017. Automatically Comparing Memory Consistency Models. In POPL. ACM, New York, NY, USA, 190-204. https://doi.org/10.1145/3009837.3009838 Google ScholarGoogle ScholarDigital LibraryDigital Library
  46. Jun Yang, Qingsong Wei, Cheng Chen, Chundong Wang, Khai Leong Yong, and Bingsheng He. 2015. NV-Tree: Reducing Consistency Cost for NVM-Based Single Level Systems. In FAST. USENIX Association, USA, 167-181.Google ScholarGoogle Scholar
  47. Yoav Zuriel, Michal Friedman, Gali Shefi, Nachshon Cohen, and Erez Petrank. 2019. Eficient Lock-free Durable Sets. Proc. ACM Program. Lang. 3, OOPSLA, Article 128 (Oct. 2019 ), 26 pages. https://doi.org/10.1145/3360554 Google ScholarGoogle ScholarDigital LibraryDigital Library

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