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Practical Model Checking on FPGAs

Published:15 July 2021Publication History
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Abstract

Software verification is an important stage of the software development process, particularly for mission-critical systems. As the traditional methodology of using unit tests falls short of verifying complex software, developers are increasingly relying on formal verification methods, such as explicit state model checking, to automatically verify that the software functions properly. However, due to the ever-increasing complexity of software designs, model checking cannot be performed in a reasonable amount of time when running on general-purpose cores, leading to the exploration of hardware-accelerated model checking. FPGAs have been demonstrated to be promising verification accelerators, exhibiting nearly three orders of magnitude speedup over software. Unfortunately, the “FPGA programmability wall,” particularly the long synthesis and place-and-route times, block the general adoption of FPGAs for model checking.

To address this problem, we designed a runtime-programmable pipeline specifically for model checkers on FPGAs to minimize the “preparation time” before a model can be checked. Our design of the successor state generator and the state validator modules enables FPGA-acceleration of model checking without incurring the time-consuming FPGA implementation stages, reducing the preparation time before checking a model from hours to less than a minute, while incurring only a 26% execution time overhead compared to model-specific implementations.

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        • Published in

          cover image ACM Transactions on Reconfigurable Technology and Systems
          ACM Transactions on Reconfigurable Technology and Systems  Volume 14, Issue 2
          June 2021
          107 pages
          ISSN:1936-7406
          EISSN:1936-7414
          DOI:10.1145/3468069
          • Editor:
          • Deming Chen
          Issue’s Table of Contents

          Copyright © 2021 Association for Computing Machinery.

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 15 July 2021
          • Accepted: 1 January 2021
          • Revised: 1 November 2020
          • Received: 1 July 2019
          Published in trets Volume 14, Issue 2

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