Abstract
Nowadays, static power consumption in chip multiprocessor (CMP) is the most crucial concern of chip designers. Power-gating is an effective approach to mitigate static power consumption particularly in low utilization. Network-on-Chip (NoC) as the backbone of multi- and many-core chips has no exception. Previous state-of-the-art techniques in power-gating desire to decrease static power consumption alongside the lack of diminution in performance of NoC. However, maintaining the performance and utilization of the power-gating approach has not yet been addressed very well. In this article, we propose TAMA (Turn-Aware Mapping & Architecture) as an effective method to boost the performance of the TooT method that was only powering on a router during turning pass or packet injection. In other words, in the TooT method, straight and eject packets pass the router via a bypass route without powering on the router. By employing meta-heuristic approaches (Genetic and Ant Colony algorithms), we develop a specific application mapping that attempts to decrease the number of turns through interconnection networks. Accordingly, the average latency of packet transmission decreases due to fewer turns. Also, by powering on turn routers in advance with lightweight hardware, the latency of sending packets diminishes. The experimental results demonstrate that our proposed approach, i.e., TAMA achieves more than 13% reduction in packet latency of NoC in comparison with TooT. Besides the packet latency, the power consumption of TAMA is reduced by about 87% compared to the traditional approach.
- Mohamed S. Abdelfattah and Vaughn Betz. 2013. The power of communication: Energy-efficient NOCS for FPGAS. In 23rd International Conference on Field-programmable Logic and Applications. IEEE, 1–8.Google Scholar
- Meisam Abdollahi and Siamak Mohammadi. 2020. Insertion loss-aware application mapping onto the optical Cube-Connected Cycles architecture. Comput. Electric. Eng. 82 (2020), 106559.Google Scholar
Cross Ref
- Meisam Abdollahi and Siamak Mohammadi. 2020. Vulnerability assessment of fault-tolerant optical network-on-chips. J. Parallel Distrib. Comput. 145 (2020), 140–159.Google Scholar
Cross Ref
- Ahmed Ben Achballah, Slim Ben Othman, and Slim Ben Saoud. 2017. Problems and challenges of emerging technology networks- on- chip: A review. Microproc. Microsyst. 53 (2017), 1–20.Google Scholar
Digital Library
- Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, and Niraj K. Jha. 2009. GARNET: A detailed on-chip network model inside a full-system simulator. In IEEE International Symposium on Performance Analysis of Systems and Software. IEEE, 33–42.Google Scholar
- Fawaz Alazemi, Arash Azizimazreah, Bella Bose, and Lizhong Chen. 2018. Routerless network-on-chip. In IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 492–503.Google Scholar
Cross Ref
- Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin, and Nor Hisham Hamid. 2017. Review of network on chip architectures. Rec. Adv. Electric. Electron. Eng. 10, 1 (2017), 4–29.Google Scholar
- Mohammad Baharloo, Rashid Aligholipour, Meisam Abdollahi, and Ahmad Khonsari. 2020. ChangeSUB: A power efficient multiple network-on-chip architecture. Comput. Electric. Eng. 83 (2020), 106578.Google Scholar
Cross Ref
- Mohammad Baharloo and Ahmad Khonsari. 2018. A low-power wireless-assisted multiple network-on-chip. Microproc. Microsyst. 63 (2018), 104–115.Google Scholar
Cross Ref
- Mohammad Baharloo, Ahmad Khonsari, Mahdi Dolati, Pouya Shiri, Masoumeh Ebrahimi, and Dara Rahmati. 2020. Traffic-aware performance optimization in Real-time wireless network on chip. Nano Commun. Netw. (2020), 100321.Google Scholar
- Djalila Belkebir and Adel Zga. 2019. Mapping and scheduling techniques in NoC: A survey of the state of the art. In International Conference on Networking and Advanced Systems (ICNAS). IEEE, 1–6.Google Scholar
Cross Ref
- Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, et al. 2008. Tile64-processor: A 64-core soc with mesh interconnect. In IEEE International Solid-state Circuits Conference–Digest of Technical Papers. IEEE, 88–598.Google Scholar
Cross Ref
- Biswajit Bhowmik, Jatindra Kumar Deka, and Santosh Biswas. 2020. Improving reliability in spidergon network on chip-microprocessors. In IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 474–477.Google Scholar
Cross Ref
- Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, and Kai Li. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques. 72–81.Google Scholar
Digital Library
- Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, et al. 2011. The gem5 simulator. ACM SIGARCH Comput. Archit. News 39, 2 (2011), 1–7.Google Scholar
Digital Library
- Mario R. Casu and Paolo Giaccone. 2017. Power-performance assessment of different DVFS control policies in NoCs. J. Parallel Distrib. Comput. 109 (2017), 193–207.Google Scholar
Digital Library
- Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, and Li-Shiuan Peh. 2013. SMART: A single-cycle reconfigurable NoC for SoC applications. In Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 338–343.Google Scholar
- Lizhong Chen and Timothy M. Pinkston. 2012. NoRD: Node-router decoupling for effective power-gating of on-chip routers. In 45th IEEE/ACM International Symposium on Microarchitecture. IEEE, 270–281.Google Scholar
- Lizhong Chen, Lihang Zhao, Ruisheng Wang, and Timothy M. Pinkston. 2014. MP3: Minimizing performance penalty for power-gating of Clos network-on-chip. In IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 296–307.Google Scholar
- Lizhong Chen, Di Zhu, Massoud Pedram, and Timothy M. Pinkston. 2015. Power punch: Towards non-blocking power-gating of NoC routers. In IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). IEEE, 378–389.Google Scholar
- Lizhong Chen, Di Zhu, Massoud Pedram, and Timothy M. Pinkston. 2016. Simulation of NoC power-gating: Requirements, optimizations, and the agate simulator. J. Parallel Distrib. Comput. 95 (2016), 69–78.Google Scholar
Digital Library
- Reetuparna Das, Satish Narayanasamy, Sudhir K. Satpathy, and Ronald G. Dreslinski. 2013. Catnap: Energy proportional multiple network-on-chip. ACM SIGARCH Comput. Archit. News 41, 3, 320–331.Google Scholar
Digital Library
- Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P. Chandrakasan, and Li-Shiuan Peh. 2014. SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. In ACM/IEEE 41st International Symposium on Computer Architecture (ISCA). IEEE, 25–36.Google Scholar
Digital Library
- Fatemeh Dehghani, Siamak Mohammadi, Behrang Barekatain, and Meisam Abdollahi. 2020. Power loss analysis in thermally-tuned nanophotonic switch for on-chip interconnect. Nano Commun. Netw. (2020), 100323.Google Scholar
- Dominic DiTomaso, Ashif Sikder, Avinash Kodi, and Ahmed Louri. 2017. Machine learning enabled power-aware network-on-chip design. In Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1354–1359.Google Scholar
Cross Ref
- Marco Dorigo, Vittorio Maniezzo, and Alberto Colorni. 1996. Ant system: optimization by a colony of cooperating agents. IEEE Trans. Syst. Man Cybern. Part B 26, 1 (1996), 29–41.Google Scholar
Digital Library
- Ahsen Ejaz, Vassilios Papaefstathiou, and Ioannis Sourdis. 2018. DDRNoC: Dual data-rate network-on-chip. ACM Trans. Archit. Code Optim. 15, 2 (2018), 1–24.Google Scholar
Digital Library
- Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, and Doug Burger. 2011. Dark silicon and the end of multicore scaling. In 38th International Symposium on Computer Architecture (ISCA). IEEE, 365–376.Google Scholar
Digital Library
- Hossein Farrokhbakht, Hadi Mardani Kamali, and Shaahin Hessabi. 2017. SMART: a scalable mapping and routing technique for power-gating in NoC routers. In 11th IEEE/ACM International Symposium on Networks-on-Chip. 1–8.Google Scholar
Digital Library
- Hossein Farrokhbakht, Hadi Mardani Kamali, and Natalie D. Enright Jerger. 2019. Muffin: Minimally-buffered zero-delay power-gating technique in on-chip routers. In IEEE/ACM International Symposium on Low Power Electronics and Design. IEEE, 1–6.Google Scholar
- Hossein Farrokhbakht, Henry Kao, and Natalie Enright Jerger. 2019. UBERNoC: Unified buffer power-efficient router for network-on-chip. In 13th IEEE/ACM International Symposium on Networks-on-Chip. 1–8.Google Scholar
Digital Library
- Hossein Farrokhbakht, Mohammadkazem Taram, Behnam Khaleghi, and Shaahin Hessabi. 2016. TooT: An efficient and scalable power-gating method for NoC routers. In 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS). IEEE, 1–8.Google Scholar
Cross Ref
- John L. Henning. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Archit. News 34, 4 (2006), 1–17.Google Scholar
Digital Library
- Joel Hestness, Boris Grot, and Stephen W. Keckler. 2010. Netrace: Dependency-driven trace-based network-on-chip simulation. In 3rd International Workshop on Network on Chip Architectures. 31–36.Google Scholar
- John Henry Holland, et al. 1992. Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence. The MIT Press.Google Scholar
- Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, and Shekhar Borkar. 2007. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro 27, 5 (2007), 51–61.Google Scholar
Digital Library
- Wei Hu, Qingsong Shi, Yonghao Wang, Kai Zhang, Jun Liu, Xiaoming Liu, and Hong Guo. 2016. An efficient task mapping algorithm with power-aware optimization for network on chip. J. Syst. Archit. 70 (2016), 48–58.Google Scholar
Digital Library
- Zeno Jonke, Stefan Habenschuss, and Wolfgang Maass. 2016. Solving constraint satisfaction problems with networks of spiking neurons. Front. Neurosci. 10 (2016), 118.Google Scholar
- Michael Jünger, Gerhard Reinelt, and Giovanni Rinaldi. 1995. The traveling salesman problem. Handb. Oper. Res. Manag. Sci. 7 (1995), 225–330.Google Scholar
- Shiming Li, Shasha Guo, Limeng Zhang, Ziyang Kang, Shiying Wang, Wei Shi, Lei Wang, and Weixia Xu. 2020. SNEAP: a fast and efficient toolchain for mapping large-scale spiking neural network onto NoC-based neuromorphic platform. In 2020 Great Lakes Symposium on VLSI. 9–14.Google Scholar
Digital Library
- Weichen Liu, Lei Yang, Weiwen Jiang, Liang Feng, Nan Guan, Wei Zhang, and Nikil Dutt. 2018. Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip. IEEE Trans. Comput. 67, 12 (2018), 1818–1834.Google Scholar
Digital Library
- Amin Mosayyebzadeh, Maziar Mehdizadeh Amiraski, and Shaahin Hessabi. 2016. Thermal and power aware task mapping on 3D Network on Chip. Comput. Electric. Eng. 51 (2016), 157–167.Google Scholar
Digital Library
- Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, and Masoumeh Ebrahimi. 2020. An overview of efficient interconnection networks for deep neural network accelerators. IEEE J. Emerg. Select. Topics Circ. Syst. 10, 3 (2020), 268–282.Google Scholar
Cross Ref
- Alireza Namazi and Meisam Abdollahi. 2017. PCG: Partially clock-gating approach to reduce the power consumption of fault-tolerant register files. In Euromicro Conference on Digital System Design (DSD). IEEE, 323–328.Google Scholar
Cross Ref
- Alireza Namazi, Meisam Abdollahi, Saeed Safari, and Siamak Mohammadi. 2017. LORAP: Low-overhead power and reliability-aware task mapping based on instruction footprint for real-time applications. In Euromicro Conference on Digital System Design (DSD). IEEE, 364–367.Google Scholar
Cross Ref
- Alireza Namazi, Meisam Abdollahi, Saeed Safari, Siamak Mohammadi, and Masoud Daneshtalab. 2016. Reliability-aware task scheduling using clustered replication for multi-core real-time systems. In 9th International Workshop on Network on Chip Architectures. 45–50.Google Scholar
Digital Library
- Alireza Namazi, Saeed Safari, Siamak Mohammadi, and Meisam Abdollahi. 2019. SORT: Semi online reliable task mapping for embedded multi-core systems. ACM Trans. Model. Perf. Eval. Comput. Syst. 4, 2 (2019), 1–25.Google Scholar
Digital Library
- Emmanuel Ofori-Attah and Michael Opoku Agyeman. 2018. A survey of power-aware Network-on-Chip design techniques. In 13th International Multi-Conference on Computing in Global Information Technology. IARIA.Google Scholar
- Ritesh Parikh, Reetuparna Das, and Valeria Bertacco. 2014. Power-aware NoCs through routing and topology reconfiguration. In 51st Design Automation Conference. 1–6.Google Scholar
Digital Library
- Ng Yen Phing, M. N. Mohd Warip, Phaklen Ehkan, R. Badlishah Ahmad, Fazrul Faiz Zakaria, and Farah Wahida Zulkefli. 2016. Towards high performance network-on-chip: A survey on enabling technologies, open issues and challenges. In 3rd International Conference on Electronic Design (ICED). IEEE, 259–263.Google Scholar
Cross Ref
- Md Farhadur Reza. 2020. Reinforcement learning based dynamic link configuration for energy-efficient NoC. In IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 468–473.Google Scholar
Cross Ref
- Md Farhadur Reza and Paul Ampadu. 2019. Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks. In 13th IEEE/ACM International Symposium on Networks-on-chip. 1–8.Google Scholar
Digital Library
- Md Farhadur Reza, Tung Thanh Le, Bappaditya De, Magdy Bayoumi, and Dan Zhao. 2018. Neuro-NoC: Energy optimization in heterogeneous many-core NoC using neural networks in dark silicon era. In IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1–5.Google Scholar
Cross Ref
- Mohammad Sadrosadati, Seyed Borna Ehsani, Hajar Falahati, Rachata Ausavarungnirun, Arash Tavakkol, Mojtaba Abaee, Lois Orosa, Yaohua Wang, Hamid Sarbazi-Azad, and Onur Mutlu. 2019. ITAP: Idle-time-aware power management for GPU execution units. ACM Trans. Archit. Code Optim. 16, 1 (2019), 1–26.Google Scholar
Digital Library
- Samira Saeidi, Ahmad Khademzadeh, and Fatemeh Vardi. 2009. Crinkle: A heuristic mapping algorithm for network on chip. IEICE Electron. Exp. 6, 24 (2009), 1737–1744.Google Scholar
Cross Ref
- Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Hoskote, Sriram Vangal, Gregory Ruhl, and Nitin Borkar. 2011. A 2 Tb/s 6*4 mesh network for a single-chip cloud computer with DVFS in 45 nm CMOS. IEEE J. Solid-state Circ. 46, 4 (2011), 757–766.Google Scholar
Cross Ref
- M. Norazizi Sham Mohd Sayuti and Leandro Soares Indrusiak. 2013. Real-time low-power task mapping in networks-on-chip. In IEEE Computer Society Symposium on VLSI (ISVLSI). IEEE, 14–19.Google Scholar
- Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, and Vladimir Stojanovic. 2012. DSENT-A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In IEEE/ACM 6th International Symposium on Networks-on-Chip. IEEE, 201–210.Google Scholar
Digital Library
- Mohammadkazem Taram, Ashish Venkat, and Dean Tullsen. 2018. Mobilizing the micro-ops: Exploiting context sensitive decoding for security and energy efficiency. In ACM/IEEE 45th International Symposium on Computer Architecture (ISCA). IEEE, 624–637.Google Scholar
Digital Library
- Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, and Axel Jantsch. 2014. Designing 2D and 3D Network-on-Chip Architectures. Springer.Google Scholar
- Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Jae-Wook Lee, Walter Lee, et al. 2002. The raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro 22, 2 (2002), 25–35.Google Scholar
Digital Library
- Sebastian Werner, Javier Navaridas, and Mikel Luján. 2016. A survey on design approaches to circumvent permanent faults in networks-on-chip. ACM Comput. Surv. 48, 4 (2016), 1–36.Google Scholar
Digital Library
- Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta. 1995. The SPLASH-2 programs: Characterization and methodological considerations. ACM SIGARCH Comput. Archit. News 23, 2, 24–36.Google Scholar
Digital Library
- Yuan Yao and Zhonghai Lu. 2016. DVFS for NoNs in CMPs: A thread voting approach. In IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 309–320.Google Scholar
- Davide Zoni and William Fornaciari. 2015. Modeling DVFS and power-gating actuators for cycle-accurate NoC-based simulators. ACM J. Emerg. Technol. Comput. Syst. 12, 3 (2015), 1–24.Google Scholar
Digital Library
Index Terms
TAMA: Turn-aware Mapping and Architecture – A Power-efficient Network-on-Chip Approach
Recommendations
Simulation of NoC power-gating
The static power consumption of networks-on-chip (NoCs) has been increasing across each technology generation. Power-gating is a very promising approach that can dramatically reduce NoC static power but may potentially cause substantial performance ...
SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers
ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and DesignDue to high aggregate idle time of Networks-on-Chip (NoCs) routers in practical applications, power-gating techniques have been proposed to combat the ever-increasing ratio of static power. Nevertheless, the sporadic packet arrivals compromise the ...
Applying partial power-gating to bit-sliced network-on-chip
In the many-core systems, network-on-chip (NoC) serves as an efficient and scalable architecture to connect numerous on-chip resources, whereas it encounters the crisis of the increasing leakage power as technology is continually scaling down. Power-...






Comments