Surendra Bommu
Abstract
Current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. Retiming is typically applied as a postprocessing step to the gate-level implementation obtained after technology mapping. This paper introduces a new sequential logic transformation which integrates retiming with logic transformations at the technology-independent level. This transformation is based on implicit retiming across logic blocks and fanout stems during logic optimization. Its application to sequential network synthesis results in the optimization of logic across register boundaries. It can be used in conjunction with any measure of circuit quality for which a fast and reliable gain estimation method can be obtained. We immplemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycle-time minimization on a set sequential benchmark circuits.
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Index Terms
Retiming-based factorization for sequential logic optimization
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Reviews
Cristiana Bolchini
Devices are growing more complex, and design methodologies are moving toward higher levels of abstraction. The authors present the results of their work in introducing retiming issues early in the design process in order to exploit the additional degrees of freedom and to reduce overhead. The main achievement consists of the possibility of performing circuit retiming during the synthesis process, specifically during the design optimization step, rather than in the last stage of the device realization. A thorough review of other approaches found in the literature explains the state of the art of circuit retiming, and highlights the limits of the current methods. In order to explain the goal of their proposed technique, the authors introduce a small but explanatory circuit example that shows the benefits of explicitly taking into account the effects of retiming on logic simplification. The next sections present the theoretical basis of the retiming operation and the algorithms used to carry it out. Several network examples help explain the concepts, allowing readers without a strong background in logic synthesis, optimization, and retiming to follow the discussion. A review of the usual delay models is presented in order to provide a complete background before introducing the theorems supporting the proposed retiming methodology. Experiments with a well-known set of benchmark circuits support the authors' work and demonstrate the advantages of introducing retiming issues at the beginning of the device realization process.
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