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Approaches for FPGA Design Assurance

Published:27 December 2021Publication History
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Abstract

Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design.

In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design.

We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.

REFERENCES

  1. [1] Adee S.. 2008. The hunt for the kill switch. IEEE Spectrum 45, 5 (2008), 3439. DOI: https://doi.org/10.1109/MSPEC.2008.4505310 Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. [2] Xiao K., Forte D., Jin Y., Karri R., Bhunia S., and Tehranipoor M.. 2016. Hardware trojans: Lessons learned after one decade of research. 22, 1 (2016), 6:1–6:23. DOI: https://doi.org/10.1145/2906147 Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. [3] Krieg Christian, Wolf Clifford, Jantsch Axel, and Zseby Tanja. 2017. Toggle MUX: How x-optimism can lead to malicious hardware. In Design Automation Conference (DAC) (2017-06). 16. DOI: https://doi.org/10.1145/3061639.3062328 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. [4] Krieg Christian, Wolf Clifford, and Jantsch Axel. 2016. Malicious LUT: A stealthy FPGA trojan injected and triggered by the design flow. In International Conference on Computer-aided Design (ICCAD) (2016-11). 18. DOI: https://doi.org/10.1145/2966986.2967054 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. [5] Swierczynski Pawel, Fyrbiak Marc, Koppe Philipp, and Paar Christof. 2015. FPGA trojans through detecting and weakening of cryptographic primitives. 34, 8 (2015), 12361249. DOI: https://doi.org/10.1109/TCAD.2015.2399455Google ScholarGoogle Scholar
  6. [6] Hastings Adam, Jensen Sean, Goeders Jeffrey, and Hutchings Brad. 2018. Using physical and functional comparisons to assure 3rd-Party IP for modern FPGAs. In International Verification and Security Workshop (IVSW) (2018-07). 8086. DOI: https://doi.org/10.1109/IVSW.2018.8494874Google ScholarGoogle Scholar
  7. [7] Wolf Clifford. 2020. Project IceStorm. Retrieved from http://www.clifford.at/icestorm/.Google ScholarGoogle Scholar
  8. [8] OneSpin. 2020. 360 EC-FPGA – OneSpin Solutions. Retrieved from /products/360-ec-fpga.Google ScholarGoogle Scholar
  9. [9] Salmani Hassan, Tehranipoor Mohammad, and Plusquellic Jim. 2012. A novel technique for improving hardware trojan detection and reducing trojan activation time. 20, 1 (2012), 112125. DOI: https://doi.org/10.1109/TVLSI.2010.2093547 Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. [10] Zhang Jie, Yuan Feng, Wei Linxiao, Liu Yannan, and Xu Qiang. 2015. VeriTrust: Verification for hardware trust. 34, 7 (2015), 11481161. DOI: https://doi.org/10.1109/TCAD.2015.2422836Google ScholarGoogle Scholar
  11. [11] He Jiaji, Zhao Yiqiang, Guo Xiaolong, and Jin Yier. 2017. Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis. 25, 10 (2017), 29392948. DOI: https://doi.org/10.1109/TVLSI.2017.2727985Google ScholarGoogle Scholar
  12. [12] Kitsos Paris, Stefanidis Kyriakos, and Voyiatzis Artemios G.. 2016. TERO-based detection of hardware trojans on FPGA implementation of the AES algorithm. In Euromicro Conference on Digital System Design (DSD) (2016-08). 678681. DOI: https://doi.org/10.1109/DSD.2016.47Google ScholarGoogle ScholarCross RefCross Ref
  13. [13] Pyrgas Lampros, Pirpilidis Filippos, Panayiotarou Aliki, and Kitsos Paris. 2017. Thermal sensor based hardware trojan detection in FPGAs. In Euromicro Conference on Digital System Design (DSD) (2017–08). 268273. https://doi.org/10.1109/DSD.2017.36Google ScholarGoogle ScholarCross RefCross Ref
  14. [14] Lecomte Maxime, Fournier Jacques, and Maurine Philippe. 2017. An on-chip technique to detect hardware trojans and assist counterfeit identification. 25, 12 (2017), 33173330. DOI: https://doi.org/10.1109/TVLSI.2016.2627525Google ScholarGoogle Scholar
  15. [15] Narasimhan Seetharam, Du Dongdong, Chakraborty Rajat Subhra, Paul Somnath, Wolff Francis, Papachristou Christos, Roy Kaushik, and Bhunia Swarup. 2010. Multiple-parameter side-channel analysis: A non-invasive hardware trojan detection approach. In International Symposium on Hardware-oriented Security and Trust (HOST) (2010–06). 1318. DOI: https://doi.org/10.1109/HST.2010.5513122Google ScholarGoogle Scholar
  16. [16] Zhang Xuehui, Ferraiuolo Andrew, and Tehranipoor Mohammad. 2013. Detection of trojans using a combined ring oscillator network and off-chip transient power analysis. 9, 3 (2013), 25:1–25:20. DOI: https://doi.org/10.1145/2491677 Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. [17] Ender Maik, Moradi Amir, and Paar Christof. 2020. The unpatchable silicon: A full break of the bitstream encryption of Xilinx 7-series FPGAs. In USENIX Conference on Security Symposium. USENIX Association, 18031819. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. [18] Yu Hoyoung, Lee Hansol, Lee Sangil, Kim Youngmin, and Lee Hyung-Min. 2018. Recent advances in FPGA reverse engineering. 7, 10 (2018), 246. DOI: https://doi.org/10.3390/electronics7100246Google ScholarGoogle Scholar
  19. [19] Matas Kaspar, La Tuan Minh, Pham Khoa Dang, and Koch Dirk. 2020. Power-hammering through glitch amplification—Attacks and mitigation. In International Symposium on Field-programmable Custom Computing Machines (FCCM) (2020–05). 6569. DOI: https://doi.org/10.1109/FCCM48280.2020.00018Google ScholarGoogle Scholar
  20. [20] Hutchings Brad L., Monson Joshua, Savory Danny, and Keeley Jared. 2014. A power side-channel-based digital to analog converter for Xilinx FPGAs. In Symposium on Field-programmable Gate Arrays (FPGA) (2014-02-26). 113116. DOI: https://doi.org/10.1145/2554688.2554770 Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. [21] Hadžić Ilija, Udani Sanjay, and Smith Jonathan M.. 1999. FPGA viruses. In Conference on Field Programmable Logic and Applications (FPL) (1999), Lysaght Patrick, Irvine James, and Hartenstein Reiner (Eds.). 291300. DOI: https://doi.org/10.1007/978-3-540-48302-1_30 Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. [22] Gaskin T., Cook H., Stirk W., Lucas R., Goeders J., and Hutchings B.. 2020. Using novel configuration techniques for accelerated FPGA aging. In 30th International Conference on Field-programmable Logic and Applications (FPL) (2020-08). 169175. DOI: https://doi.org/10.1109/FPL50879.2020.00037ISSN: 1946-1488.Google ScholarGoogle ScholarCross RefCross Ref
  23. [23] 2020. Symbiflow/Prjuray. https://github.com/SymbiFlow/prjuray.Google ScholarGoogle Scholar
  24. [24] 2020. Symbiflow/Prjxray. https://github.com/SymbiFlow/prjxray.Google ScholarGoogle Scholar
  25. [25] Gnad D. R. E., Rapp S., Krautter J., and Tahoori M. B.. 2018. Checking for electrical level security threats in bitstreams for multi-tenant FPGAs. In International Conference on Field-programmable Technology (FPT) (2018–12). 286289. DOI: https://doi.org/10.1109/FPT.2018.00055Google ScholarGoogle ScholarCross RefCross Ref
  26. [26] La Tuan Minh, Matas Kaspar, Grunchevski Nikola, Pham Khoa Dang, and Koch Dirk. 2020. FPGADefender: Malicious self-oscillator scanning for Xilinx ultrascale + FPGAs. 13, 3 (2020), 15:1–15:31. DOI: https://doi.org/10.1145/3402937 Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. [27] Kępa K., Morgan F., Kościuszkiewicz K., Braun L., Hübner M., and Becker J.. 2010. Design assurance strategy and toolset for partially reconfigurable FPGA systems. 4, 1 (2017), 4:1–4:26. DOI: https://doi.org/10.1145/1857927.1857931 Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. [28] Wolf Clifford. 2021. Yosys Open SYnthesis Suite. Retrieved from https://github.com/YosysHQ/yosys.Google ScholarGoogle Scholar
  29. [29] McKay Brendan D. and Piperno Adolfo. 2014. Practical graph isomorphism, II. 60 (2014), 94112. DOI: https://doi.org/10.1016/j.jsc.2013.09.003 Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. [30] Cordella L. P., Foggia P., Sansone C., and Vento M.. 2004. A (sub)graph isomorphism algorithm for matching large graphs. 26, 10 (2004), 13671372. DOI: https://doi.org/10.1109/TPAMI.2004.75Google ScholarGoogle Scholar

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        • Published in

          cover image ACM Transactions on Reconfigurable Technology and Systems
          ACM Transactions on Reconfigurable Technology and Systems  Volume 15, Issue 3
          September 2022
          353 pages
          ISSN:1936-7406
          EISSN:1936-7414
          DOI:10.1145/3508070
          • Editor:
          • Deming Chen
          Issue’s Table of Contents

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 27 December 2021
          • Accepted: 1 October 2021
          • Revised: 1 August 2021
          • Received: 1 April 2021
          Published in trets Volume 15, Issue 3

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