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Protecting Network-on-Chip Intellectual Property Using Timing Channel Fingerprinting

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Published:08 February 2022Publication History
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Abstract

The theft of Intellectual property (IP) is a serious security threat for all businesses that are involved in the creation of IP. In this article, we consider such attacks against IP for Network-on-Chip (NoC) that are commonly used as a popular on-chip scalable communication medium for Multiprocessor System-on-Chip. As a protection mechanism, we propose a timing channel fingerprinting method and show its effectiveness by implementing five different solutions using this method. We also provide a formal proof of security of the proposed method. We show that the proposed technique provides better security and requires much lower hardware overhead (64%–74% less) compared to an existing NoC IP security solution without affecting the normal packet latency or degrading the NoC performance.

REFERENCES

  1. [1] Abdalla Michel, Fouque Pierre-Alain, and Pointcheval David. 2005. Password-based authenticated key exchange in the three-party setting. In Proceedings of the 8th International Conference on Theory and Practice in Public Key Cryptography. Springer-Verlag, 6584. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. [2] United States National Institute of Standards and Technology (NIST). 2001. Announcing the Advanced Encryption Standard (AES). November 26, 2001. https://nvlpubs.nist.gov/nistpubs/fips/nist.fips.197.pdf.Google ScholarGoogle Scholar
  3. [3] Toshihiro Katashita and Akashi Satoh. 2013. Electronic Circuit Component Authenticity Determination Method . US Patent 2013/0127442, May 23, 2013.Google ScholarGoogle Scholar
  4. [4] Barni Mauro, Bartolini Franco, Rosa Alessia De, and Piva Alessandro. 1999. Capacity of the watermark channel: How many bits can be hidden within a digital image? In Proceedings of the Society of Photo-Optical Instrumentation Engineers (SPIE). 3657.Google ScholarGoogle ScholarCross RefCross Ref
  5. [5] Becker Georg T., Fyrbiak Marc, and Kison Christian. 2017. Hardware Obfuscation: Techniques and Open Challenges. Springer International Publishing, 105123.Google ScholarGoogle Scholar
  6. [6] Biswas Arnab Kumar. 2020. Network-on-chip intellectual property protection using circular path–based fingerprinting. J. Emerg. Technol. Comput. Syst. 17, 1, Article 4 (Sept. 2020), 22 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. [7] Biswas Arnab Kumar, Ghosal Dipak, and Nagaraja Shishir. 2017. A survey of timing channels and countermeasures. ACM Comput. Surv. 50, 1, Article 6 (Mar. 2017), 39 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. [8] Caldwell A. E., Choi Hyun-Jin, Kahng A. B., Mantik S., Potkonjak M., Qu Gang, and Wong J. L.. 2004. Effective iterative techniques for fingerprinting design IP. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 23, 2 (Feb. 2004), 208215. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. [9] Catania Vincenzo, Mineo Andrea, Monteleone Salvatore, Palesi Maurizio, and Patti Davide. 2017. Improving energy efficiency in wireless network-on-chip architectures. J. Emerg. Technol. Comput. Syst. 14, 1, Article 9 (2017). Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. [10] Chang C. H. and Zhang L.. 2014. A blind dynamic fingerprinting technique for sequential circuit intellectual property protection. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 33, 1 (Jan. 2014), 7689. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. [11] World Semiconductor Council. 2018. Winning the Battle Against Counterfeit Semiconductor Products. White Paper. http://www.semiconductorcouncil.org/wp-content/uploads/2018/06/WSC-Anti-Counterfeiting-White-Paper-May-2018-Update.pdf.Google ScholarGoogle Scholar
  12. [12] Juergen Teich and Daniel Ziener. 2007. Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark. US Patent 2007/0220263, September 20, 2007.Google ScholarGoogle Scholar
  13. [13] Fan Y. C.. 2008. Testing-based watermarking techniques for intellectual-property identification in soc design. IEEE Trans. Instrument. Measure. 57, 3 (Mar. 2008), 467479.Google ScholarGoogle ScholarCross RefCross Ref
  14. [14] Kahng A. B., Lach J., Mangione-Smith W. H., Mantik S., Markov I. L., Potkonjak M., Tucker P., Wang H., and Wolfe G.. 2001. Constraint-based watermarking techniques for design IP protection. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 20, 10 (Oct. 2001), 12361252. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. [15] Kahng Andrew B., Mantik Stefanus, Markov Igor L., Potkonjak Miodrag, Tucker Paul, Wang Huijuan, and Wolfe Gregory. 1998. Robust IP watermarking methodologies for physical design. In Proceedings of the 35th Annual Design Automation Conference (DAC’98). ACM, New York, NY, 782787. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. [16] Liu Bao and Qu Gang. 2016. VLSI supply chain security risks and mitigation techniques: A survey. Integr. VLSI J. 55 (2016), 438448.Google ScholarGoogle ScholarCross RefCross Ref
  17. [17] Liu Q., Ji W., Chen Q., and Mak T.. 2016. IP protection of mesh NoCs using square spiral routing. IEEE Trans. Very Large Scale Integr. Syst. 24, 4 (Apr. 2016), 15601573.Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. [18] MarketsandMarkets. 2019. Semiconductor Intellectual Property (IP) Market by Design IP (Processor IP, Interface IP, Memory IP), IP Source (Royalty and Licensing), Vertical (Consumer Electronics, Telecom, Industrial, Automotive, Commercial), and Region—Global Forecast to 2024. Retrieved from https://www.marketsandmarkets.com/Market-Reports/semiconductor-silicon-intellectual-property-ip-market-651.html.Google ScholarGoogle Scholar
  19. [19] Qu Gang. 2001. Keyless public watermarking for intellectual property authentication. In Information Hiding, Moskowitz Ira S. (Ed.). Springer, Berlin, 96111. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. [20] Sugihara Ryo. 2001. Practical capacity of digital watermarks. In Information Hiding, Moskowitz Ira S. (Ed.). Springer, Berlin, 316330. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. [21] Worm F., Ienne P., Thiran P., and micheli G. de. 2002. An adaptive low-power transmission scheme for on-chip networks. In Proceedings of the 15th International Symposium on System Synthesis, 2002.92100.Google ScholarGoogle ScholarDigital LibraryDigital Library

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        • Published in

          cover image ACM Transactions on Embedded Computing Systems
          ACM Transactions on Embedded Computing Systems  Volume 21, Issue 2
          March 2022
          187 pages
          ISSN:1539-9087
          EISSN:1558-3465
          DOI:10.1145/3514174
          • Editor:
          • Tulika Mitra
          Issue’s Table of Contents

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 8 February 2022
          • Accepted: 1 November 2021
          • Revised: 1 September 2021
          • Received: 1 May 2021
          Published in tecs Volume 21, Issue 2

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