Abstract
The theft of Intellectual property (IP) is a serious security threat for all businesses that are involved in the creation of IP. In this article, we consider such attacks against IP for Network-on-Chip (NoC) that are commonly used as a popular on-chip scalable communication medium for Multiprocessor System-on-Chip. As a protection mechanism, we propose a timing channel fingerprinting method and show its effectiveness by implementing five different solutions using this method. We also provide a formal proof of security of the proposed method. We show that the proposed technique provides better security and requires much lower hardware overhead (64%–74% less) compared to an existing NoC IP security solution without affecting the normal packet latency or degrading the NoC performance.
- [1] . 2005. Password-based authenticated key exchange in the three-party setting. In Proceedings of the 8th International Conference on Theory and Practice in Public Key Cryptography. Springer-Verlag, 65–84. Google Scholar
Digital Library
- [2] United States National Institute of Standards and Technology (NIST). 2001. Announcing the Advanced Encryption Standard (AES). November 26, 2001. https://nvlpubs.nist.gov/nistpubs/fips/nist.fips.197.pdf.Google Scholar
- [3] Toshihiro Katashita and Akashi Satoh. 2013. Electronic Circuit Component Authenticity Determination Method . US Patent 2013/0127442, May 23, 2013.Google Scholar
- [4] . 1999. Capacity of the watermark channel: How many bits can be hidden within a digital image? In Proceedings of the Society of Photo-Optical Instrumentation Engineers (SPIE). 3657.Google Scholar
Cross Ref
- [5] . 2017. Hardware Obfuscation: Techniques and Open Challenges. Springer International Publishing, 105–123.Google Scholar
- [6] . 2020. Network-on-chip intellectual property protection using circular path–based fingerprinting. J. Emerg. Technol. Comput. Syst. 17, 1, Article
4 (Sept. 2020), 22 pages. Google ScholarDigital Library
- [7] . 2017. A survey of timing channels and countermeasures. ACM Comput. Surv. 50, 1, Article
6 (Mar. 2017), 39 pages. Google ScholarDigital Library
- [8] . 2004. Effective iterative techniques for fingerprinting design IP. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 23, 2 (
Feb. 2004), 208–215. Google ScholarDigital Library
- [9] . 2017. Improving energy efficiency in wireless network-on-chip architectures. J. Emerg. Technol. Comput. Syst. 14, 1, Article
9 (2017). Google ScholarDigital Library
- [10] . 2014. A blind dynamic fingerprinting technique for sequential circuit intellectual property protection. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 33, 1 (
Jan. 2014), 76–89. Google ScholarDigital Library
- [11] World Semiconductor Council. 2018. Winning the Battle Against Counterfeit Semiconductor Products. White Paper. http://www.semiconductorcouncil.org/wp-content/uploads/2018/06/WSC-Anti-Counterfeiting-White-Paper-May-2018-Update.pdf.Google Scholar
- [12] Juergen Teich and Daniel Ziener. 2007. Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark. US Patent 2007/0220263, September 20, 2007.Google Scholar
- [13] . 2008. Testing-based watermarking techniques for intellectual-property identification in soc design. IEEE Trans. Instrument. Measure. 57, 3 (
Mar. 2008), 467–479.Google ScholarCross Ref
- [14] . 2001. Constraint-based watermarking techniques for design IP protection. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 20, 10 (
Oct. 2001), 1236–1252. Google ScholarDigital Library
- [15] . 1998. Robust IP watermarking methodologies for physical design. In Proceedings of the 35th Annual Design Automation Conference (DAC’98). ACM, New York, NY, 782–787. Google Scholar
Digital Library
- [16] . 2016. VLSI supply chain security risks and mitigation techniques: A survey. Integr. VLSI J. 55 (2016), 438–448.Google Scholar
Cross Ref
- [17] . 2016. IP protection of mesh NoCs using square spiral routing. IEEE Trans. Very Large Scale Integr. Syst. 24, 4 (
Apr. 2016), 1560–1573.Google ScholarDigital Library
- [18] . 2019. Semiconductor Intellectual Property (IP) Market by Design IP (Processor IP, Interface IP, Memory IP), IP Source (Royalty and Licensing), Vertical (Consumer Electronics, Telecom, Industrial, Automotive, Commercial), and Region—Global Forecast to 2024. Retrieved from https://www.marketsandmarkets.com/Market-Reports/semiconductor-silicon-intellectual-property-ip-market-651.html.Google Scholar
- [19] . 2001. Keyless public watermarking for intellectual property authentication. In Information Hiding, (Ed.). Springer, Berlin, 96–111. Google Scholar
Digital Library
- [20] . 2001. Practical capacity of digital watermarks. In Information Hiding, (Ed.). Springer, Berlin, 316–330. Google Scholar
Digital Library
- [21] . 2002. An adaptive low-power transmission scheme for on-chip networks. In Proceedings of the 15th International Symposium on System Synthesis, 2002.92–100.Google Scholar
Digital Library
Index Terms
Protecting Network-on-Chip Intellectual Property Using Timing Channel Fingerprinting
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