skip to main content

Generating circuits with generators

Published:31 August 2022Publication History
Skip Abstract Section

Abstract

The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away.

We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.

References

  1. Christiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, and Marco Gerards. 2010. Cλ aSH: Structural Descriptions of Synchronous Hardware using Haskell. In Proceedings of the 13th Conference on Digital System Design (DSD 2010). Lille, France. 714–721. https://doi.org/10.1109/DSD.2010.21 Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Christiaan Baaij and Jan Kuper. 2014. Using Rewriting to Synthesize Functional Languages to Digital Circuits. In Proceedings of the Fourteenth Symposium on Trends in Functional Programming (TFP 2014), Jay McCarthy (Ed.). Springer, Provo, UT, USA. 17–33. https://doi.org/10.1007/978-3-642-45340-3_2 Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, and Krste Asanović. 2012. Chisel: constructing hardware in a scala embedded language. In Design Automation Conference 2012 (DAC 2012). San Francisco, CA, USA. 1212–1221. https://doi.org/10.1145/2228360.2228584 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. David Bacon, Rodric Rabbah, and Sunil Shukla. 2013. FPGA Programming for the Masses: The Programmability of FPGAs Must Improve If They Are to Be Part of Mainstream Computing.. Queue, 11, 2 (2013), Feb., 40–52. https://doi.org/10.1145/2436696.2443836 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Jeffrey M. Bell, Françoise Bellegarde, and James Hook. 1997. Type-driven defunctionalization. In Proceedings of the 1997 ACM SIGPLAN International Conference on Functional Programming, Mads Tofte (Ed.) (SIGPLAN Notices, Vol. 32, No. 8). ACM Press, Amsterdam, The Netherlands. 25–37. https://doi.org/10.1145/258948.258953 Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Dariusz Biernacki, Maciej Piróg, Piotr Polesiuk, and Filip Sieczkowski. 2020. Binders by Day, Labels by Night: Effect Instances via Lexically Scoped Handlers. In Proceedings of the Forty-Seventh Annual ACM Symposium on Principles of Programming Languages, Lars Birkedal (Ed.). ACM Press, Cascals, Portugal. 29 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason H Anderson, Stephen Brown, and Tomasz Czajkowski. 2011. LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2011). ACM, New York, NY, USA. 33–36. https://doi.org/10.1145/1950413.1950423 Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Xavier Clerc and Arsenly Alekseyev. 2018. Hardcaml. https://github.com/janestreet/hardcaml Google ScholarGoogle Scholar
  9. Edsger W. Dijkstra. 1968. Go To Statement Considered Harmful. Commun. ACM, 11, 3 (1968), March, 147–148. https://doi.org/10.1145/362929.362947 Letter to the editor. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Cormac Flanagan, Amr Sabry, Bruce F. Duba, and Matthias Felleisen. 1993. The Essence of Compiling with Continuations. In Proceedings of the ACM SIGPLAN’93 Conference on Programming Languages Design and Implementation, David W. Wall (Ed.) (SIGPLAN Notices, Vol. 28, No 6). ACM Press, Albuquerque, New Mexico. 237–247. https://doi.org/10.1145/173262.155113 Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Mike Gordon. 1995. The semantic challenge of Verilog HDL. In Proceedings of the Tenth Annual IEEE Symposium on Logic in Computer Science, Andre Scedrov (Ed.). IEEE Computer Society, San Diego, CA, USA. 136–145. https://doi.org/10.1109/LICS.1995.523251 Google ScholarGoogle ScholarCross RefCross Ref
  12. Samuel Greengard. 2020. Will RISC-V revolutionize computing? Commun. ACM, 63, 5 (2020), April, 30–32. https://doi.org/10.1145/3386377 Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. John L. Hennessy and David A. Patterson. 2019. A New Golden Age for Computer Architecture. Commun. ACM, 62, 2 (2019), Jan., 48–60. https://doi.org/10.1145/3282307 Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. 1998. HD44780U (LCD-II) Dot Matrix Liquid Crystal Display Controller/Driver. Google ScholarGoogle Scholar
  15. C.A.R. Hoare. 1975. Recursive Data Structures. International Journal of Computer and Information Sciences, 4, 2 (1975), 105–132. https://doi.org/10.1007/BF00976239 Google ScholarGoogle ScholarCross RefCross Ref
  16. Paul Hudak. 1996. Building Domain-Specific Embedded Languages. Comput. Surveys, 28, 4 (1996), Dec., 196. https://doi.org/10.1145/242224.242477 Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. 2018. IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language. https://doi.org/10.1109/IEEESTD.2018.8299595 Google ScholarGoogle ScholarCross RefCross Ref
  18. 2019. IEEE Standard for VHDL Language Reference Manual. https://doi.org/10.1109/IEEESTD.2019.8938196 Google ScholarGoogle ScholarCross RefCross Ref
  19. Thomas Johnsson. 1985. Lambda Lifting: Transforming Programs to Recursive Equations. In Functional Programming Languages and Computer Architecture, Jean-Pierre Jouannaud (Ed.) (Lecture Notes in Computer Science, 201). Springer-Verlag, Nancy, France. 190–203. https://doi.org/10.1007/3-540-15975-4_37 Google ScholarGoogle ScholarCross RefCross Ref
  20. Barbara Liskov, Alan Snyder, Russell Atkinson, and Craig Schaffert. 1977. Abstraction Mechanisms in CLU. Commun. ACM, 20, 8 (1977), Aug., 564–576. https://doi.org/10.1145/359763.359789 Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Jason Lowe-Power and Christopher Nitta. 2019. The Davis In-Order (DINO) CPU: A Teaching-Focused RISC-V CPU Design. In Proceedings of the Workshop on Computer Architecture Education. ACM, Phoenix, AZ, USA. 8 pages. https://doi.org/10.1145/3338698.3338892 Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Geoffrey Mainland. 2007. Why It’s Nice to Be Quoted: Quasiquoting for Haskell. In Proceedings of the ACM SIGPLAN Workshop on Haskell (Haskell ’07). Association for Computing Machinery, Freiburg, Germany. 73–82. https://doi.org/10.1145/1291201.1291211 Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Marek Materzok. 2022. Reproduction Package for Article ’Generating Circuits with Generators’. https://doi.org/10.5281/zenodo.6874025 Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. George H. Mealy. 1955. A method for synthesizing sequential circuits. The Bell System Technical Journal, 34, 5 (1955), 1045–1079. https://doi.org/10.1002/j.1538-7305.1955.tb03788.x Google ScholarGoogle ScholarCross RefCross Ref
  25. Don Mills and Clifford E Cummings. 1999. RTL coding styles that yield simulation and synthesis mismatches. In The 9th Annual Synopsys (& EPIC) Users Group Meeting (SNUG’99). San Jose, CA, USA. 16 pages. Google ScholarGoogle Scholar
  26. Edward F. Moore. 1956. Gedanken-Experiments on Sequential Machines. In Automata Studies, Claude Shannon and John McCarthy (Eds.). 34, Princeton University Press, Princeton, NJ. 129–153. https://doi.org/10.1515/9781400882618-006 Google ScholarGoogle ScholarCross RefCross Ref
  27. Shayan Najd, Sam Lindley, Josef Svenningsson, and Philip Wadler. 2016. Everything old is new again: quoted domain-specific languages. In Proceedings of the 2016 ACM SIGPLAN Workshop on Partial Evaluation and Program Manipulation, Martin Erwig and Tiark Rompf (Eds.). ACM Press, St. Petersburg, FL, USA. 25–36. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Keiko Nakata and Tarmo Uustalu. 2010. Resumptions, Weak Bisimilarity and Big-Step Semantics for While with Interactive I/O: An Exercise in Mixed Induction-Coinduction. In Proceedings of the Seventh Workshop on Structural Operational Semantics (SOS 2010), Luca Aceto and Pawel Sobocinski (Eds.) (EPTCS, Vol. 32). Paris, France. 57–75. https://doi.org/10.4204/EPTCS.32.5 Google ScholarGoogle ScholarCross RefCross Ref
  29. Jesse op den Brouw. 2012. Simple HD44780 Driver. https://opencores.org/projects/hd44780_driver Google ScholarGoogle Scholar
  30. Charles Papon. 2017. SpinalHDL: An alternative hardware description language. Feb., https://archive.fosdem.org/2017/schedule/event/spinal_hdl/ Presented on the Free and Open Source Software Developers’ European Meeting in 2017 (FOSDEM 2017). Google ScholarGoogle Scholar
  31. Christian Pilato and Fabrizio Ferrandi. 2013. Bambu: A modular framework for the high level synthesis of memory-intensive applications. In 2013 23rd International Conference on Field programmable Logic and Applications (FPL 2013). Porto, Portugal. 1–4. https://doi.org/10.1109/FPL.2013.6645550 Google ScholarGoogle ScholarCross RefCross Ref
  32. Gordon Plotkin and John Power. 2004. Computational Effects and Operations: An Overview. Electronic Notes in Theoretical Computer Science, 73 (2004), Oct., 149–163. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Gordon D. Plotkin. 1975. Call-by-name, Call-by-value and the λ -calculus. Theoretical Computer Science, 1 (1975), 125–159. https://doi.org/10.1016/0304-3975(75)90017-1 Google ScholarGoogle ScholarCross RefCross Ref
  34. John C. Reynolds. 1972. Definitional Interpreters for Higher-Order Programming Languages. In Proceedings of 25th ACM National Conference. Boston, Massachusetts. 717–740. https://doi.org/10.1145/800194.805852 Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Soujanna Sarkar, Shashank Dabral, Praveen K Tiwari, and Raj S Mitra. 2009. Lessons and experiences with high-level synthesis. IEEE Design & Test of Computers, 26, 4 (2009), 34–45. https://doi.org/10.1109/MDT.2009.84 Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Neil Schemenauer, Tim Peters, and Magnus Lie Hetland. 2001. Simple Generators. https://www.python.org/dev/peps/pep-0255/ Google ScholarGoogle Scholar
  37. Ofer Shacham, Omid Azizi, Megan Wachs, Wajahat Qadeer, Zain Asgar, Kyle Kelley, John Stevenson, Stephen Richardson, Mark Horowitz, Benjamin Lee, Alexandre Solomatnikov, and Amin Firoozshahian. 2011. Rethinking Digital Design: Why Design Must Change. Micro, IEEE, 30 (2011), 9–24. https://doi.org/10.1109/MM.2010.81 Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, and Miodrag Milanovic. 2019. Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 4 pages. https://doi.org/10.1109/FCCM.2019.00010 Google ScholarGoogle ScholarCross RefCross Ref
  39. Lenny Truong and Pat Hanrahan. 2019. A golden age of hardware description languages: Applying programming language techniques to improve design productivity. In 3rd Summit on Advances in Programming Languages (SNAPL 2019). 136, Providence, RI, USA. 1–21. https://doi.org/10.4230/LIPIcs.SNAPL.2019.7 Google ScholarGoogle Scholar
  40. 2019. The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2019121, Andrew Waterman and Krste Asanović (Eds.). Google ScholarGoogle Scholar
  41. Stephen Zekany, Jielun Tan, James Connelly, and Ronald Dreslinski. 2021. RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA. In Proceedings of the 52nd ACM Technical Symposium on Computer Science Education. ACM, New York, NY, USA. 1096–1102. https://doi.org/10.1145/3408877.3432472 Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Generating circuits with generators

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader
        About Cookies On This Site

        We use cookies to ensure that we give you the best experience on our website.

        Learn more

        Got it!