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Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation

Published:10 May 2023Publication History
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Abstract

Checkpoint-based debugging flows have recently been developed that allow the user to move the design state back and forth between an FPGA and a simulator. They provide a softwarelike debugging experience by combining the speed of hardware execution and the full visibility of simulation. However, they assume the entire system state can be moved to a simulator, limiting them to self-contained systems. In this article, we present StateLink, a transaction-based co-simulation framework that allows part of the system (the task) to run in a simulator and still interact with other system components that reside in hardware. StateLink allows tasks to remain connected to and active in the overall hardware system after their state is moved to a simulator. This extends the functionality of checkpoint-based debugging frameworks to designs with external I/Os and significantly speeds up the simulation of tasks that are part of a large system. StateLink typically adds no timing overhead and a modest hardware area overhead. The total area overhead of using the proposed flow on a Memcached system is only 13%. This flow allows the user to benefit from both the hardware speedup of ∼1M× and the StateLink speedup of up to 44× versus full system simulation.

REFERENCES

  1. [1] Angepat Hari, Eads Gage, Craik Christopher, and Chiou Derek. 2010. NIFD: Non-intrusive FPGA debugger—Debugging FPGA ‘threads’ for rapid HW/SW systems prototyping. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL’10). 356359. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. [2] Asaad Sameh, Bellofatto Ralph, Brezzo Bernard, Haymes Chuck, Kapur Mohit, Parker Benjamin, Roewer Thomas, Saha Proshanta, Takken Todd, and Tierno José. 2012. A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’12). 153162. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. [3] Attia Sameh and Betz Vaughn. 2020. Feel free to interrupt: Safe task stopping to enable FPGA checkpointing and context switching. ACM Trans. Reconfig. Technol. Syst. 13, 1 (2020), 127.Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. [4] Attia Sameh and Betz Vaughn. 2020. StateMover: Combining simulation and hardware execution for efficient FPGA debugging. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’20). 175185.Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. [5] Attia Sameh and Betz Vaughn. 2020. StateReveal: Enabling checkpointing of FPGA designs with buried state. In Proceedings of the International Conference on Field-Programmable Technologies (FPT’20).Google ScholarGoogle ScholarCross RefCross Ref
  6. [6] Attia Sameh and Betz Vaughn. 2021. StateLink: FPGA system debugging via flexible simulation/hardware integration. In Proceedings of the International Conference on Field-Programmable Technologies (FPT’21).Google ScholarGoogle ScholarCross RefCross Ref
  7. [7] Attia Sameh and Betz Vaughn. 2022. Stop and look: A novel checkpointing and debugging flow for FPGAs. IEEE Trans. Comput. (2022), 11.Google ScholarGoogle Scholar
  8. [8] Banerjee Somnath and Gupta Tushar. 2012. Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’12). 115122.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. [9] Bussa Pavan K., Goeders Jeffrey, and Wilton Steven J. E.. 2017. Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’17). 14. Google ScholarGoogle ScholarCross RefCross Ref
  10. [10] Cheng X., Ruan A. W., Liao Y. B., Li P., and Huang H. C.. 2010. A run-time RTL debugging methodology for FPGA-based co-simulation. In Proceedings of the International Conference on Communications, Circuits and Systems (ICCCAS’10). 891895. Google ScholarGoogle ScholarCross RefCross Ref
  11. [11] Kasindorf Alan “Dormando”. 2018. Memcached—A Distributed Memory Object Caching System. Retrieved June 1, 2019 from http://memcached.org/.Google ScholarGoogle Scholar
  12. [12] Eslami Fatemeh and Wilton Steven J. E.. 2014. Incremental distributed trigger insertion for efficient FPGA debug. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’14). 14. Google ScholarGoogle ScholarCross RefCross Ref
  13. [13] Foster Harry. 2020. Wilson Research Group Functional Verification Study: FPGA Functional Verification Trend Report. White Paper. Wilson Research Group and Mentor, A Siemens Business.Google ScholarGoogle Scholar
  14. [14] Goeders Jeffrey and Wilton Steven J. E.. 2017. Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 36, 1 (2017), 8396. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. [15] Noronha Daniel Holanda, Zhao Ruizhe, Goeders Jeff, Luk Wayne, and Wilton Steven J. E.. 2019. On-chip FPGA debug instrumentation for machine learning applications. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’19). 110115. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. [16] Huang Chung-Yang, Yin Yu-Fan, Hsu Chih-Jen, Huang Thomas B., and Chang Ting-Mao. 2011. SoC HW/SW verification and validation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC’11). 297300. Google ScholarGoogle ScholarCross RefCross Ref
  17. [17] Hung Eddie and Wilton Steven J. E.. 2013. Scalable signal selection for post-silicon debug. IEEE Trans. Very Large Scale Integr. Syst. 21, 6 (2013), 11031115. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. [18] Hung Eddie and Wilton Steven J. E.. 2014. Incremental trace-buffer insertion for FPGA debug. IEEE Trans. Very Large Scale Integr. Syst. 22, 4 (2014), 850863. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. [19] Hutchings Brad L. and Keeley Jared. 2014. Rapid post-map insertion of embedded logic analyzers for Xilinx FPGAs. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM’14). 7279. Google ScholarGoogle ScholarCross RefCross Ref
  20. [20] Hutchings B. L. and Nelson B. E.. 2001. Unifying simulation and execution in a design environment for FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 9, 1 (2001), 201205.Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. [21] Intel, Inc. 2015. Quartus Prime Handbook Volume 3: Verification.Google ScholarGoogle Scholar
  22. [22] Iskander Yousef, Patterson Cameron, and Craven Stephen. 2014. High-level abstractions and modular debugging for FPGA design validation. ACM Trans. Reconfig. Technol. Syst. 7, 1 (2014), 2:1–2:22. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. [23] Kim Donggyu, Celio Christopher, Karandikar Sagar, Biancolin David, Bachrach Jonathan, and Asanovic Krste. 2018. DESSERT: Debugging RTL effectively with state snapshotting for error replays across trillions of cycles. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’18). 7679. Google ScholarGoogle ScholarCross RefCross Ref
  24. [24] Li Changgong, Schwarz Alexander, and Hochberger Christian. 2016. A readback based general debugging framework for soft-core processors. In Proceedings of the International Conference on Computer Design (ICCD’16). 568575. Google ScholarGoogle ScholarCross RefCross Ref
  25. [25] Sidler David and Eguro Ken. 2016. Debugging framework for FPGA-based soft processors. In Proceedings of teh International Conference on Field-Programmable Technology (FPT’16). 165168. Google ScholarGoogle ScholarCross RefCross Ref
  26. [26] Tzimpragos Georgios, Cheng Da, Tapp Stephanie, Jayadev Balakrishna, and Majumdar Amitava. 2016. Application debug in FPGAs in the presence of multiple asynchronous clocks. In Proceedings of the International Conference on Field-Programmable Technology (FPT’16). 189192. Google ScholarGoogle ScholarCross RefCross Ref
  27. [27] Xilinx. 2016. HLS Implementation of Memcached Pipeline. Retrieved June 1, 2019 from https://github.com/Xilinx/HLx_Examples/tree/master/Acceleration/memcached.Google ScholarGoogle Scholar
  28. [28] Xilinx, Inc. 2016. PG144: AXI GPIO v2.0. Xilinx, Inc.Google ScholarGoogle Scholar
  29. [29] Xilinx, Inc. 2016. PG172: Integrated Logic Analyzer. Xilinx, Inc.Google ScholarGoogle Scholar
  30. [30] Xilinx, Inc. 2020. UG1483: Model Composer and System Generator User Guide. Xilinx, Inc.Google ScholarGoogle Scholar
  31. [31] Yang Sangjun, Shim Heejun, Yang Wooseung, and Kyung Chong-Min. 2004. A new RTL debugging methodology in FPGA-based verification platform. In Proceedings of the IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (APASIC’04). 180183. Google ScholarGoogle ScholarCross RefCross Ref

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  1. Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation

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    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 16, Issue 2
      June 2023
      451 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/3587031
      • Editor:
      • Deming Chen
      Issue’s Table of Contents

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 10 May 2023
      • Online AM: 1 August 2022
      • Accepted: 25 July 2022
      • Revised: 22 June 2022
      • Received: 6 April 2022
      Published in trets Volume 16, Issue 2

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