Abstract
Checkpoint-based debugging flows have recently been developed that allow the user to move the design state back and forth between an FPGA and a simulator. They provide a softwarelike debugging experience by combining the speed of hardware execution and the full visibility of simulation. However, they assume the entire system state can be moved to a simulator, limiting them to self-contained systems. In this article, we present StateLink, a transaction-based co-simulation framework that allows part of the system (the task) to run in a simulator and still interact with other system components that reside in hardware. StateLink allows tasks to remain connected to and active in the overall hardware system after their state is moved to a simulator. This extends the functionality of checkpoint-based debugging frameworks to designs with external I/Os and significantly speeds up the simulation of tasks that are part of a large system. StateLink typically adds no timing overhead and a modest hardware area overhead. The total area overhead of using the proposed flow on a Memcached system is only 13%. This flow allows the user to benefit from both the hardware speedup of ∼1M× and the StateLink speedup of up to 44× versus full system simulation.
- [1] . 2010. NIFD: Non-intrusive FPGA debugger—Debugging FPGA ‘threads’ for rapid HW/SW systems prototyping. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL’10). 356–359. Google Scholar
Digital Library
- [2] . 2012. A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’12). 153–162. Google Scholar
Digital Library
- [3] . 2020. Feel free to interrupt: Safe task stopping to enable FPGA checkpointing and context switching. ACM Trans. Reconfig. Technol. Syst. 13, 1 (2020), 1–27.Google Scholar
Digital Library
- [4] . 2020. StateMover: Combining simulation and hardware execution for efficient FPGA debugging. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’20). 175–185.Google Scholar
Digital Library
- [5] . 2020. StateReveal: Enabling checkpointing of FPGA designs with buried state. In Proceedings of the International Conference on Field-Programmable Technologies (FPT’20).Google Scholar
Cross Ref
- [6] . 2021. StateLink: FPGA system debugging via flexible simulation/hardware integration. In Proceedings of the International Conference on Field-Programmable Technologies (FPT’21).Google Scholar
Cross Ref
- [7] . 2022. Stop and look: A novel checkpointing and debugging flow for FPGAs. IEEE Trans. Comput. (2022), 1–1.Google Scholar
- [8] . 2012. Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’12). 115–122.Google Scholar
Digital Library
- [9] . 2017. Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’17). 1–4. Google Scholar
Cross Ref
- [10] . 2010. A run-time RTL debugging methodology for FPGA-based co-simulation. In Proceedings of the International Conference on Communications, Circuits and Systems (ICCCAS’10). 891–895. Google Scholar
Cross Ref
- [11] . 2018. Memcached—A Distributed Memory Object Caching System. Retrieved June 1, 2019 from http://memcached.org/.Google Scholar
- [12] . 2014. Incremental distributed trigger insertion for efficient FPGA debug. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’14). 1–4. Google Scholar
Cross Ref
- [13] . 2020. Wilson Research Group Functional Verification Study: FPGA Functional Verification Trend Report.
White Paper . Wilson Research Group and Mentor, A Siemens Business.Google Scholar - [14] . 2017. Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 36, 1 (2017), 83–96. Google Scholar
Digital Library
- [15] . 2019. On-chip FPGA debug instrumentation for machine learning applications. In Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA’19). 110–115. Google Scholar
Digital Library
- [16] . 2011. SoC HW/SW verification and validation. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC’11). 297–300. Google Scholar
Cross Ref
- [17] . 2013. Scalable signal selection for post-silicon debug. IEEE Trans. Very Large Scale Integr. Syst. 21, 6 (2013), 1103–1115. Google Scholar
Digital Library
- [18] . 2014. Incremental trace-buffer insertion for FPGA debug. IEEE Trans. Very Large Scale Integr. Syst. 22, 4 (2014), 850–863. Google Scholar
Digital Library
- [19] . 2014. Rapid post-map insertion of embedded logic analyzers for Xilinx FPGAs. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM’14). 72–79. Google Scholar
Cross Ref
- [20] . 2001. Unifying simulation and execution in a design environment for FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 9, 1 (2001), 201–205.Google Scholar
Digital Library
- [21] . 2015. Quartus Prime Handbook Volume 3: Verification.Google Scholar
- [22] . 2014. High-level abstractions and modular debugging for FPGA design validation. ACM Trans. Reconfig. Technol. Syst. 7, 1 (2014), 2:1–2:22. Google Scholar
Digital Library
- [23] . 2018. DESSERT: Debugging RTL effectively with state snapshotting for error replays across trillions of cycles. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’18). 76–79. Google Scholar
Cross Ref
- [24] . 2016. A readback based general debugging framework for soft-core processors. In Proceedings of the International Conference on Computer Design (ICCD’16). 568–575. Google Scholar
Cross Ref
- [25] . 2016. Debugging framework for FPGA-based soft processors. In Proceedings of teh International Conference on Field-Programmable Technology (FPT’16). 165–168. Google Scholar
Cross Ref
- [26] . 2016. Application debug in FPGAs in the presence of multiple asynchronous clocks. In Proceedings of the International Conference on Field-Programmable Technology (FPT’16). 189–192. Google Scholar
Cross Ref
- [27] . 2016. HLS Implementation of Memcached Pipeline. Retrieved June 1, 2019 from https://github.com/Xilinx/HLx_Examples/tree/master/Acceleration/memcached.Google Scholar
- [28] 2016. PG144: AXI GPIO v2.0. Xilinx, Inc.Google Scholar
- [29] 2016. PG172: Integrated Logic Analyzer. Xilinx, Inc.Google Scholar
- [30] 2020. UG1483: Model Composer and System Generator User Guide. Xilinx, Inc.Google Scholar
- [31] . 2004. A new RTL debugging methodology in FPGA-based verification platform. In Proceedings of the IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (APASIC’04). 180–183. Google Scholar
Cross Ref
Index Terms
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation
Recommendations
StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging
FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysDebugging consumes a large portion of FPGA design time, and with the growing complexity of traditional FPGA systems and the additional verification challenges posed by multiple FPGAs interacting within data centers, debugging productivity is becoming ...
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)
FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysTo address the increasing demand of System-on-Chip (SoC) for high performance applications and IP programmability, specialized SoC with custom logic is developed in a single chip or multi-chip system. Like any other SoC platforms, early software ...
Debugging in the brave new world of reconfigurable hardware
ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating SystemsSoftware and hardware development cycles have traditionally been quite distinct. Software allows post-deployment patches, which leads to a rapid development cycle. In contrast, hardware bugs that are found after fabrication are extremely costly to fix (...






Comments