Abstract
Tasks in modern embedded systems such as automotive and avionics communicate among each other using shared data towards achieving the desired functionality of the whole system. In commodity platforms, cores communicate data through the shared memory hierarchy and correctness is maintained by a cache coherence protocol. Recent works investigated the deployment of coherence protocols in real-time systems and showed significant performance improvements. Nonetheless, we find these works to require modifications to commodity coherence protocols, assume simple in-order pipelines, and most importantly suffer from significant latency delays due to coherence interference along with average performance degradation. In this work, we propose
- [1] . 1981. Performance analysis of high-speed digital buses for multiprocessing systems. In Proceedings of the 8th Annual Symposium on Computer Architecture. 107–133.Google Scholar
- [2] . 2019. Cache where you want! Reconciling predictability and coherent caching. arXiv preprint arXiv:1909.05349 (2019).Google Scholar
- [3] . 2016. Contention-free execution of automotive applications on a clustered many-core platform. In IEEE Euromicro Conference on Real-Time Systems (ECRTS).Google Scholar
Cross Ref
- [4] . 2016. Reconciling the tension between hardware isolation and data sharing in mixed-criticality, multicore systems. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [5] . 1988. Fair Arbitration Technique for a Split Transaction Bus in a Multiprocessor Computer System.
US Patent 4,785,394. Google Scholar - [6] . 2016. QorIQ T2080 Reference Manual.
Also supports T2081. Document Number: T2080RM. Rev. 3, 11/2016. Google Scholar - [7] . 2015. A survey on cache management mechanisms for real-time embedded systems. ACM Comput. Surv. (2015).Google Scholar
Digital Library
- [8] . 2015. On the design and evaluation of a real-time operating system for cache-coherent multicore architectures. ACM SIGOPS Oper. Syst. Rev. (2015).Google Scholar
- [9] . 2018. A comparative study of predictable dram controllers. ACM Transactions on Embedded Computing Systems (TECS) (2018).Google Scholar
Digital Library
- [10] . 2017. Communication centric design in complex automotive embedded systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik.Google Scholar
- [11] . 2009. Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [12] . 2018. On the off-chip memory latency of real-time systems: Is DDR DRAM really the best option?. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [13] . 2020. Discriminative coherence: Balancing performance and latency bounds in data-sharing multi-core real-time systems. In Euromicro Conference on Real-Time Systems (ECRTS). 1–22.Google Scholar
- [14] . 2017. Predictable cache coherence for multi-core real-time systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).Google Scholar
- [15] . 2016. Criticality- and requirement-aware bus arbitration for multi-core mixed criticality systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).Google Scholar
- [16] . 2018. Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2018).Google Scholar
Cross Ref
- [17] . 2018. Shedding the shackles of time-division multiplexing. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [18] . 2011. Computer Architecture: A Quantitative Approach. Elsevier.Google Scholar
Digital Library
- [19] . 2020. The best of all worlds: Improving predictability at the performance of conventional coherence with no protocol modifications. In 2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 218–230.Google Scholar
Cross Ref
- [20] . 2020. Designing predictable cache coherence protocols for multi-core real-time systems. IEEE Trans. Comput. (2020).Google Scholar
- [21] . 2021. A systematic approach to achieving tight worst-case latency and high-performance under predictable cache coherence. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 1–12.Google Scholar
Cross Ref
- [22] . 2019. CARP: A data communication mechanism for multi-core mixed-criticality systems. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [23] . 2011. Bus-aware multicore WCET analysis through TDMA offset bounds. In Euromicro Conference on Real-Time Systems (ECRTS).Google Scholar
Digital Library
- [24] . 1996. Fast First-come First Served Arbitration Method.
US Patent 5,574,867. Google Scholar - [25] . 2017. Allowing shared libraries while supporting hardware isolation in multicore real-time systems. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS).Google Scholar
- [26] . 2010. Shared data caches conflicts reduction for WCET computation in multi-core architectures. In International Conference on Real-Time and Network Systems.Google Scholar
- [27] . 2013. Real-time cache management framework for multi-core architectures. In IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS).Google Scholar
- [28] . 2012. Why on-chip cache coherence is here to stay. Communications of ACM (2012).Google Scholar
Digital Library
- [29] . 2009. Hardware support for WCET analysis of hard real-time multicore systems. ACM SIGARCH Computer Architecture News (2009).Google Scholar
Digital Library
- [30] . 2008. Coscheduling of CPU and I/O transactions in COTS-based embedded systems. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [31] . 2003. Performance analysis of arbitration policies for SoC communication architectures. Design Automation for Embedded Systems (2003).Google Scholar
Digital Library
- [32] . 1995. A new approach for the verification of cache coherence protocols. IEEE Transactions on Parallel and Distributed Systems (1995).Google Scholar
- [33] . 2020. Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence. In IEEE Design Automation and Test in Europe (DATE). 1–4.Google Scholar
- [34] . 2018. Civil Certification of Multi-core Processing Systems in Commercial Avionics.Google Scholar
- [35] . 2009. Towards time-predictable data caches for chip-multiprocessors. In Springer International Workshop on Software Technologies for Embedded and Ubiquitous Systems (IFIP).Google Scholar
- [36] . 2019. Modeling cache coherence to expose interference. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik.Google Scholar
- [37] . 2020. On how to identify cache coherence: Case of the NXP QorIQ T4240. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020). Schloss Dagstuhl-Leibniz-Zentrum für Informatik.Google Scholar
- [38] . 1999. Implementing Snooping on a Split-transaction Computer System Bus.
US Patent 5,978,874. Google Scholar - [39] . 2011. A primer on memory consistency and cache coherence. Synthesis Lectures on Computer Architecture (2011).Google Scholar
Cross Ref
- [40] . 2017. Hourglass: Predictable time-based cache coherence protocol for dual-critical multi-core systems. (2017).Google Scholar
- [41] . 2019. Enabling predictable, simultaneous and coherent data sharing in mixed criticality systems. (2019).Google Scholar
- [42] . 2011. Optimizing tunable WCET with shared resource allocation and arbitration in hard real-time multicore systems. In IEEE Real-Time Systems Symposium (RTSS).Google Scholar
- [43] . 2002. Communication Handling in Integrated Modular Avionics.
US Patent App. 09/821,601. Google Scholar - [44] . 2015. Parallelism-aware memory interference delay analysis for COTS multicore systems. In Euromicro Conference on Real-Time Systems (ECRTS).Google Scholar
Digital Library
- [45] . 2010. Intel® quickpath interconnect architectural features supporting scalable system architectures. In IEEE Symposium on High Performance Interconnects.Google Scholar
Index Terms
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems
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