Abstract
A memory controller manages the flow of data to and from attached memory devices. The order in which a set of contending memory requests from different tasks are serviced significantly influences the rate of progress and completion times of these tasks. This in turn may affect the Quality-of-Service (QoS) delivered by these tasks. In this article, we focus towards the design of a QoS-aware memory controller targeted towards soft real-time systems. The proposed memory controller tries to generate an urgency-based schedule for the contending memory requests based on the allowable response time latencies associated with each request. The objective is to improve task-level response time predictability while maximizing acquired QoS. Exhaustive experiments carried out using real memory traces and standard simulation tools exhibit the practical efficacy of the proposed memory controller design.
- [1] . 2011. Memory Controllers for Real-time Embedded Systems. Springer.Google Scholar
Digital Library
- [2] . 2008. Real-time scheduling using credit-controlled static-priority arbitration. In 14th IEEE International Conference on Embedded and Real-time Computing Systems and Applications. IEEE, 3–14.Google Scholar
Digital Library
- [3] . 2012. DDR3 SDRAM specification. JESD79- (2012).Google Scholar
- [4] . 2021. A soft real-time memory request scheduler for phase change memory systems. In IEEE 27th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). IEEE, 109–118.Google Scholar
Cross Ref
- [5] . 2010. Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. In ACM SIGARCH Computer Architecture News, Vol. 40. IEEE, 1–12.Google Scholar
- [6] . 2011. Benchmarking Modern Multiprocessors. Princeton University.Google Scholar
Digital Library
- [7] . 2011. The gem5 simulator. ACM SIGARCH Computer Architecture News 39, 2 (2011), 1–7.Google Scholar
Digital Library
- [8] . 2014. An evaluation of high-level mechanistic core models. ACM Trans. Archit. Code Optim.
DOI: DOI: Google ScholarDigital Library
- [9] . 2020. Improved multi-core real-time task scheduling of reconfigurable systems with energy constraints. IEEE Access 8 (2020), 95698–95713.Google Scholar
Cross Ref
- [10] . 2014. A mixed critical memory controller using bank privatization and fixed priority scheduling. In IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications. IEEE, 1–10.Google Scholar
Cross Ref
- [11] . 2017. A globally arbitrate analyzable memory controllerd memory tree for mixed-time-criticality systems. IEEE Trans. Comput. 66, 2 (2017), 212–225.Google Scholar
Digital Library
- [12] . 2017. A requests bundling DRAM controller for mixed-criticality systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 247–258.Google Scholar
- [13] . 2001. MiBench: A free, commercially representative embedded benchmark suite. In 4th Annual IEEE International Workshop on Workload Characterization. IEEE, 3–14.Google Scholar
- [14] . 2015. A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 307–316.Google Scholar
- [15] . 2017. PMC: A requirement-aware DRAM controller for multicore mixed criticality systems. ACM Trans. Embed. Comput. Syst. 16, 4 (2017), 1–28.Google Scholar
Digital Library
- [16] . 2010. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann.Google Scholar
Digital Library
- [17] . 2014. A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study. In Real-Time Systems Symposium (RTSS). IEEE, 207–217.Google Scholar
- [18] . 2021. Joint algorithm of message fragmentation and no-wait scheduling for time-sensitive networks. IEEE/CAA J. Automat. Sinic. 8, 2 (2021), 478–490.Google Scholar
Cross Ref
- [19] . 2018. A model predictive scheduling algorithm in real-time control systems. IEEE/CAA J. Automat. Sinic. 5, 2 (2018), 471–478.Google Scholar
Cross Ref
- [20] . 2015. A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 317–326.Google Scholar
- [21] . 2010. Thread cluster memory scheduling: Exploiting differences in memory access behavior. In 43rd Annual IEEE/ACM International Symposium on Microarchitecture. IEEE, 65–76.Google Scholar
- [22] . 2014. A rank-switching, open-row DRAM controller for time-predictable systems. In 26th Euromicro Conference on Real-Time Systems (ECRTS). IEEE, 27–38.Google Scholar
Digital Library
- [23] . 2016. Modeling and verification of dynamic command scheduling for real-time memory controllers. In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 1–12.Google Scholar
- [24] . 2016. LAMS: A latency-aware memory scheduling policy for modern DRAM systems. In IEEE 35th International Performance Computing and Communications Conference (IPCCC). IEEE, 1–8.Google Scholar
Cross Ref
- [25] . 2007. Memory performance attacks: Denial of memory service in multi-core systems. In 16th USENIX Security Symposium on USENIX Security Symposium. USENIX Association.Google Scholar
- [26] . 2007. Stall-time fair memory access scheduling for chip multiprocessors. In 40th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 146–160.Google Scholar
- [27] . 2008. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems. In ACM SIGARCH Computer Architecture News, Vol. 36. IEEE Computer Society, 63–74.Google Scholar
- [28] . 2009. An analyzable memory controller for hard real-time CMPs. IEEE Embed. Syst. Lett. 1, 4 (2009), 86–90.Google Scholar
Digital Library
- [29] . 2011. PRET DRAM controller: Bank privatization for predictability and temporal isolation. In 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, 99–108.Google Scholar
Digital Library
- [30] . 2000. Memory access scheduling. In ACM SIGARCH Computer Architecture News, Vol. 28. ACM, 128–138.Google Scholar
- [31] . 2011. DRAMSim2: A cycle accurate memory system simulator. IEEE Comput. Archit. Lett. 10, 1 (2011), 16–19.Google Scholar
Digital Library
- [32] . 2017. Scrubbing-aware placement for reliable FPGA systems. IEEE Trans. Emerg. Topics Comput. 8, 3 (2017), 564–576.Google Scholar
Cross Ref
- [33] . 2014. Dynamic low-power reconfiguration of real-time systems with periodic and probabilistic tasks. IEEE Trans. Autom. Sci. Eng. 12, 1 (2014), 258–271.Google Scholar
Cross Ref
- [34] . 2014. PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 155–166.Google Scholar
Index Terms
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems
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