Abstract
Although NAND flash memory has the advantages of small size, low-power consumption, shock resistance, and fast access speed, NAND flash memory still faces the problems of “out-of-place updates,” “garbage collection,” and “unbalanced execution time” due to its hardware limitations. Usually, a flash translation layer (FTL) can maintain the mapping cache (in limited DRAM space) to store the frequently accessed address mapping for “out-of-place updates” and maintain the read/write buffer (in limited DRAM space) to store the frequently accessed data for “garbage collection” and “unbalanced execution time”. In this article, we will propose a write-related and read-related DRAM allocation strategy inside solid-state drives (SSDs). The design idea behind the write-related DRAM allocation method is to calculate the suitable DRAM allocation for the write buffer and the write mapping cache by building a statistical model with a minimum expected value of writes for NAND flash memory. To further reduce reads in NAND flash memory, the design idea behind the read-related DRAM allocation method is to adopt a cost-benefit policy to reallocate the proper DRAM space from the write buffer and the write mapping cache to the read buffer and the read mapping cache, respectively. According to the experimental results, we can demonstrate that the proposed write-related and read-related DRAM allocation strategy can reduce more reads/writes in NAND flash memory than other methods to improve the response time.
- [1] 2020. SNIA IOTTA Trace Repository.Google Scholar
- [2] . 2017. Log-buffer aware cache replacement policy for flash storage devices. IEEE Transactions on Consumer Electronics 63, 1 (2017), 77–84.Google Scholar
Digital Library
- [3] . 1988. Nonlinear Regression Analysis and Its Applications, Vol. 2. Wiley, New York.Google Scholar
Cross Ref
- [4] . 2002. An adaptive striping architecture for flash memory storage systems of embedded systems. In Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE, 187–196.Google Scholar
- [5] . 2019. HCFTL: A locality-aware page-level flash translation layer. In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition (DATE’19). IEEE, 590–593.Google Scholar
Cross Ref
- [6] . 2020. WPA: Write pattern aware hybrid disk buffer management for improving lifespan of NAND flash memory. IEEE Transactions on Consumer Electronics 66, 2 (2020), 193–202.Google Scholar
Cross Ref
- [7] . 2020. Fair write attribution and allocation for consolidated flash cache. In Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’20). 1063–1076.Google Scholar
Digital Library
- [8] . 2002. SPC Trace File Format Specification.Google Scholar
- [9] . 2019. Extending SSD lifespan with comprehensive non-volatile memory-based write buffers. Journal of Computer Science and Technology 34 (
1 2019), 113–132. Google ScholarCross Ref
- [10] . 2009. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. ACM SIGPLAN Notices 44, 3 (2009), 229–240.Google Scholar
Digital Library
- [11] . 2015. PASS: A proactive and adaptive SSD buffer scheme for data-intensive workloads. In Proceedings of the IEEE International Conference on Networking, Architecture and Storage (NAS’15). 54–63.Google Scholar
Cross Ref
- [12] . 2017. Reinforcement learning-assisted garbage collection to mitigate long-tail latency in SSD. ACM Transactions on Embedded Computing Systems 16, 5s (2017), 1–20.Google Scholar
Digital Library
- [13] . 2018. Dynamic management of key states for reinforcement learning-assisted garbage collection to reduce long tail latency in SSD. In Proceedings of the 55th Annual Design Automation Conference. 1–6.Google Scholar
Digital Library
- [14] . 2019. Q-value prediction for reinforcement learning assisted garbage collection to reduce long tail latency in SSD. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 10 (2020), 2240–2253.
DOI: Google ScholarCross Ref
- [15] . 2017. Understanding storage traffic characteristics on enterprise virtual desktop infrastructure. In Proceedings of the 10th ACM International Systems and Storage Conference. 1–11.Google Scholar
Digital Library
- [16] . 2019. HAML-SSD: A hardware accelerated hotness-aware machine learning based SSD management. In Proceedings of the 38th IEEE/ACM International Conference on Computer-Aided Design (ICCAD’19). Institute of Electrical and Electronics Engineers, Inc., 8942140.Google Scholar
Cross Ref
- [17] . 2020. MLCache: A space-efficient cache scheme based on reuse distance and machine learning for NVMe SSDs. In Proceedings of the 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD’20). 1–9.Google Scholar
Digital Library
- [18] . 2018. Marvell Demonstrates Artificial Intelligence SSD Controller Architecture Solution. https://www.marvell.com/company/newsroom/marvell-demonstrates-artificial-intelligence-ssd-controller-architecture-solution.html.Google Scholar
- [19] . 2008. Write off-loading: Practical power management for enterprise storage. ACM Transactions on Storage 4, 3 (2008), 1–23.Google Scholar
Digital Library
- [20] . 1993. The LRU-K page replacement algorithm for database disk buffering. ACM SIGMOD Record 22, 2 (1993), 297–306.Google Scholar
Digital Library
- [21] . 2017. A method for reducing garbage collection overhead of SSD using machine learning algorithms. In Proceedings of theInternational Conference on Information and Communication Technology Convergence (ICTC’17). 775–777.Google Scholar
Cross Ref
- [22] . 2022. Unifying temporal and spatial locality for cache management inside SSDs. In Proceedings of the2022 Design, Automation and Test in Europe Conference and Exhibition (DATE’22). 891–896. Google Scholar
Cross Ref
- [23] . 1952. A Value for n-Person Games.Google Scholar
- [24] . 1994. 2q: A low overhead high performance buffer management replacement algoritm. In Proceedings of the 20th International Conference on Very Large Databases. Santiago, Chile, 439–450.Google Scholar
- [25] . 2010. An adaptive partitioning scheme for DRAM-based cache in solid state drives. In Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST’10). IEEE, 1–12.Google Scholar
Digital Library
- [26] . 2019. 13.5 A 512Gb 3-bit/Cell 3D flash memory on 128-Wordline-Layer with 132MB/s write performance featuring circuit-under-array technology. In Proceedings of the IEEE International Solid State Circuits Conference (ISSCC’19). 218–220.Google Scholar
Cross Ref
- [27] . 2020. Fuzzy fairness controller for NVMe SSDs. In Proceedings of the 34th ACM International Conference on Supercomputing. 1–12.Google Scholar
Digital Library
- [28] . 2019. Learning-assisted write latency optimization for mobile storage. In Proceedings of the IEEE 25th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA’19).Google Scholar
Cross Ref
- [29] . 2020. SciPy 1.0: Fundamental algorithms for scientific computing in Python. Nature Methods 17, 3 (2020), 261–272. Google Scholar
Cross Ref
- [30] . 2018. Efficient SSD caching by avoiding unnecessary writes using machine learning. In Proceedings of the 47th International Conference on Parallel Processing. 1–10.Google Scholar
Digital Library
- [31] . 2019. Maximizing I/O throughput and minimizing performance variation via reinforcement learning based I/O merging for SSDs. IEEE Trans. Comput. 69, 1 (2019), 72–86.Google Scholar
Digital Library
- [32] . 2019. Reinforcement learning based background segment cleaning for log-structured file system on mobile devices. In Proceedings of the IEEE International Conference on Embedded Software and Systems (ICESS’19).Google Scholar
Cross Ref
- [33] . 2019. Reducing garbage collection overhead in SSD based on workload prediction. In Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage’19).Google Scholar
Digital Library
- [34] . 2019. An adaptive read-write partitioning flash translation layer algorithm. IEEE Access 7 (2019), 179063–179073.Google Scholar
Cross Ref
- [35] . 2017. PR-LRU: A novel buffer replacement algorithm based on the probability of reference for flash memory. IEEE Access 5 (2017), 12626–12634.Google Scholar
Cross Ref
- [36] . 2019. A correlation-aware page-level FTL to exploit semantic links in workloads. IEEE Transactions on Parallel and Distributed Systems 30, 4 (2019), 723–737. Google Scholar
Digital Library
Index Terms
A Write-Related and Read-Related DRAM Allocation Strategy Inside Solid-State Drives (SSDs)
Recommendations
Short-random request absorbing structure with volatile DRAM buffer and nonvolatile NAND flash memory
CEA'09: Proceedings of the 3rd WSEAS international conference on Computer engineering and applicationsThis paper is to design a short-random request absorbing structure which can be constructed with volatile DRAM buffer and nonvolatile flash memory chips. Specifically, major weakness of NAND flash memory mostly comes from frequent short and random ...
PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems
RTSS '11: Proceedings of the 2011 IEEE 32nd Real-Time Systems SymposiumDue to its properties of high density, in-place update, and low standby power, phase change memory (PCM) becomes a promising main memory alternative in embedded systems. On the other hand, NAND flash memory is widely used as a secondary storage and has ...
Leveraging intra-page update diversity for mitigating write amplification in SSDs
ICS '20: Proceedings of the 34th ACM International Conference on SupercomputingA solid state drive (SSD) receives requests in multiple of sectors from the host system, which are then mapped to logical pages, the basic I/O units of the flash memory. As the SSD receives requests in sector units, the sectors in a logical page tend to ...






Comments