Abstract
In this on going research paper, we present our work on the compiler support for an AI-oriented SIMD Extension, called SPARROW. The SPARROW hardware design has been developed during a recently defended, awardwinning Master Thesis and is targeting Cobham Gaisler's space processors Leon3 and NOEL-V. We present the compiler support we have included in two compiler toolchains, gcc and llvm as well as a SIMD intrinsics library for easy programmability. Compiler modifications are kept to minimum in order to enable incremental qualification of the toolchains. We present our experience working with the two compilers and performance results for the two compilers on top an FPGA implementation of the target space processor.
- M. Solé and L. Kosmidis, "SPARROW: A Low-Cost Hardware/ Software Co-designed SIMD Microarchitecture for AI Operations in Space Processors," in Design, Automation and Test in Europe Conference and Exhibition (DATE), 2022.Google Scholar
- Linux Foundation, "RISC-V Forum: Vector and Machine Learning." https://events.linuxfoundation.org/riscv-forumvector- and-machine-learning.Google Scholar
- Marc Solé, Leonidas Kosmidis, "RISCV Forum: Vector and Machine Learning." https://events.linuxfoundation.org/riscv-forum-vector-andmachine- learning/program/schedule/.Google Scholar
- M. Solé and L. Kosmidis, "SPARROW source code repository," 2021. https://gitlab.bsc.es/msolebon/sparrow.Google Scholar
Recommendations
A compiler framework for extracting superword level parallelism
PLDI '12SIMD (single-instruction multiple-data) instruction set extensions are quite common today in both high performance and embedded microprocessors, and enable the exploitation of a specific type of data parallelism called SLP (Superword Level Parallelism). ...
Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture
This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, ...
A time-predictable VLIW processor and its compiler support
Time predictability is an important requirement for real-time embedded application domains such as automotive, air transportation, and multimedia processing. However, the architectural design of modern microprocessors mainly concentrates on improving ...






Comments