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Exploiting superword level parallelism with multimedia instruction sets

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Saman AmarasingheAuthors Info & Claims

ACM SIGPLAN Notices, Volume 35, Issue 5

Pages 145 - 156

https://doi.org/10.1145/358438.349320

Published: 01 May 2000 Publication History

Abstract

Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general purpose microprocessors. This added functionality comes primarily with the addition of short SIMD instructions. Unfortunately, access to these instructions is limited to in-line assembly and library calls. Generally, it has been assumed that vector compilers provide the most promising means of exploiting multimedia instructions. Although vectorization technology is well understood, it is inherently complex and fragile. In addition, it is incapable of locating SIMD-style parallelism within a basic block.

In this paper we introduce the concept of Superword Level Parallelism (SLP),a novel way of viewing parallelism in multimedia and scientific applications. We believe SLPP is fundamentally different from the loop level parallelism exploited by traditional vector processing, and therefore demands a new method of extracting it. We have developed a simple and robust compiler for detecting SLPP that targets basic blocks rather than loop nests. As with techniques designed to extract ILP, ours is able to exploit parallelism both across loop iterations and within basic blocks. The result is an algorithm that provides excellent performance in several application domains. In our experiments, dynamic instruction counts were reduced by 46%. Speedups ranged from 1.24 to 6.70.

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Chen JYao WLi J(2025)Parallel optimization techniques for ultra-large scale refined numerical simulations on Chinese supercomputersCluster Computing10.1007/s10586-024-05057-328:8Online publication date: 19-Aug-2025
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Xiao YAhmed NCapotă MMa GWillke TNazarian SBogdan P(2025)A Graph-Based Learning Framework for Compiler Loop Auto-VectorizationIntelligent Computing10.34133/icomputing.01134Online publication date: 2-Jun-2025
https://doi.org/10.34133/icomputing.0113
Zhang TChen GPan WZheng ZSun GZhang X(2025)REFIT: Improve Code Efficiency via Binary Level Loop Optimization2025 10th International Conference on Computer and Communication System (ICCCS)10.1109/ICCCS65393.2025.11069474(252-257)Online publication date: 18-Apr-2025
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Index Terms

Exploiting superword level parallelism with multimedia instruction sets
1. Computer systems organization
  1. Architectures
    1. Serial architectures
  2. Embedded and cyber-physical systems
    1. Embedded systems

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