1 PREFACE
The International Conference on Field-Programmable Technology (FPT) is widely considered to be the premier conference series on reconfigurable technology in the Asia-Pacific region. In 2021, the 20th event in a series was planned to be held on-location in Auckland. However, the Covid-19 pandemic made a traditional in-presence conference impossible, and imposed a purely virtual mode of presentation and discussion.
Despite these difficulties, the topics of FPT remain as current as ever. Field programmable devices such as FPGAs offer the advantages of dedicated hardware, e.g., in terms of performance or power efficiency, but with an almost software-like flexibility and ease-of-use. This makes them a highly interesting implementation alternative for domains where the performance or flexibility of off-the-shelf computing platforms such as CPUs or GPUs do not suffice, but the use of fully application-specific chips (ASICs) is not possible, e.g., due to their very high non-recurring costs and the extreme design effort required to target current silicon fabrication technologies.
Reconfigurable technology encompasses a wide range of research topics that must be addressed to advance the field. These include tools and design techniques, architectures for field-programmable systems, and device technology for field-programmable chips. And, last, but not least, a study of how the technology can be leveraged in practice to improve applications, turning the potential technology benefits into actual gains for the end users.
With this wide range of topics, and despite the virtual conference mode, FPT 2021 attracted 129 submissions across its four tracks. After a thorough reviewing process, which included a rebuttal phase and at least three reviews for the research papers, 27 contributions could be accepted as full papers (21% acceptance rate), and 14 as short papers (32% overall acceptance rate).
After the conference, we invited the best eight papers from the FPT conference to submit extended versions of their work to ACM TRETS. Four author groups accepted this invitation and provided new manuscripts that underwent the full TRETS review-and-revision process. Of the new manuscripts provided, three were revised sufficiently to achieve acceptance in time for inclusion into this special issue:
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA
Drone/UAV detection is an important task for applications including surveillance, defense, and multi-drone self-localization and formation control. Single-shot multi-box detectors (SSD) using CNNs can efficiently detect and localize various objects in an input image. However, its high demand for computation and memory storage poses challenges on resource-constrained devices, such as drones or UAVs. This paper co-designed and co-optimized an algorithm and hardware for energy-efficient drone detection on resource-constrained FPGA devices. Low-precision quantization and dual-data rate operations for DSP are employed to improve the inference throughput. The proposed design achieves a high mAP of 88.42% on the multi-drone dataset, as well as 1.1-8.7x better energy efficiency than prior works.
QiCells: A Modular RFSoC-Based Approach to Interface Superconducting Quantum Bits
Quantum computing will be a revolutionary option for another kind of processing element in future heterogeneous computing systems. At the heart of quantum computing lie quantum bits (qubits), preferably in a large number, which require a careful design of the interface between the classical computer architecture and the attached quantum processor, protecting signal integrity with respect to single channels, as well as supporting scaling of the signal count. This paper presents an RFSoC-based qubit control system and its modular FPGA firmware design. It features QiCells, each containing all the logic necessary to interact with a single superconducting qubit, including a custom-built RISC-V-based sequencer. Synchronization and data exchange between the cells is facilitated by using a special star-point structure. The system's correct operation is demonstrated by interfacing to an actual superconducting five-qubit chip.
Toward Software-Like Debugging for FPGAs via Checkpointing and Transaction-Based Co-Simulation
Checkpoint-based debugging flows have recently been developed that allow the user to move the design state back and forth between an FPGA and a simulator, enabling the benefits of combining the speed of hardware execution with the full visibility of software simulation. However, previous flows usually assume that the complete system state is moved to the simulator, limiting them to self-contained systems. This paper presents StateLink, a transaction-based co-simulation framework that allows a selected part of the system (the task) to run in the simulator, but continue to interact with the other active system components that still reside in hardware. This extends the functionality of checkpoint-based debugging frameworks to designs with external I/Os, which cannot easily be moved to the software simulator, and significantly speeds up the simulation of tasks that are part of a larger system. StateLink achieves a speedup of up to 44x versus full system simulation, without any timing overhead, and incurring only a 13% area overhead.
We would like to thank all of the authors for their efforts to improve their highly-rated FPT papers even further into the excellent TRETS articles that follow this introduction. Additional thanks are due to the reviewers for providing the insightful comments that guided the authors to refine their manuscripts into the final forms included here. And of course, none of this would have been possible without the continuous support of TRETS Editor-in-Chief Deming Chen, assisted by the Editorial Associate Megan Shuler and Associate Managing Editor Angelique Ly. Last but not least, we would also like to thank Oliver Sinnen, the general chair of FPT 2021, for making the event possible in the first place.
We hope you can now enjoy the selected papers and look forward to seeing you, hopefully in-person, at one of the next FPT conferences!
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