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Scheduling time-constrained instructions on pipelined processors

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Published:01 January 2001Publication History
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Abstract

In this work we investigate the problem of scheduling instructions on idealized microprocessors with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latency constraints. A latency of lij specifies that there must be at least lij time-steps between the completion time of instruction i and the start time of instruction j. A latency of lij=−1 can be used to specify that j may be scheduled concurrently with i but not earlier. We present a generic algorithm that runs in O(n2lognα(n)+ne) time, given n instructions and e edges in the precedence DAG, where α(n) is the functional inverse of the Ackermann function. Our algorithm can be used to construct feasible schedules for various classes of instances, including instances with the following configurations: (1) one pipeline, with individual release-times and deadlines and where the latencies between instructions are restricted to 0 and 1; (2) m pipelines, with individual release-times and deadlines, and monotone-interval order precedences; (3) two pipelines with latencies of −1 or 0, and release-times and deadlines; (4) one pipeline, latencies of 0 or 1 and individual processing times that are at least one; (5) m pipelines, intree precedences, constant latencies, and deadlines; (6) m pipelines, outtree precedences, constant latencies, and release-times. For instances with deadlines, optimal schedules that minimize the maximal tardiness can be constructed using binary search, in O(log n) iterations of our algorithm. We obtain our results using backward scheduling, a very general relaxation method, which extends, unifies, and clarifies many previous results on instruction scheduling for pipelined and parallel machines.

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            cover image ACM Transactions on Programming Languages and Systems
            ACM Transactions on Programming Languages and Systems  Volume 23, Issue 1
            Jan. 2001
            103 pages
            ISSN:0164-0925
            EISSN:1558-4593
            DOI:10.1145/383721
            Issue’s Table of Contents

            Copyright © 2001 ACM

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            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 1 January 2001
            Published in toplas Volume 23, Issue 1

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