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Architecture of a VLSI multiple ISA emulator

Published:01 December 1984Publication History
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Abstract

This paper describes the architecture of a microprogrammed processor currently under development that addresses specific program objectives. These objectives include system throughput, ISA flexibility and software transportability. The design project is at the stage of completion of the architecture and the initial stages of VLSI chip design. Three candidate ISAs are scheduled to be implemented in a prototype form in the near future. While it is too early to report on results as they relate to the objectives it is believed that the overall architecture will remain as described.

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  1. Architecture of a VLSI multiple ISA emulator

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 15, Issue 4
              MICRO 17: Proceedings of the Seventeenth Annual Microprogramming Workshop
              Dec. 1984
              302 pages
              ISSN:1050-916X
              DOI:10.1145/384281
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 17: Proceedings of the 17th annual workshop on Microprogramming
                December 1984
                325 pages

              Copyright © 1984 Author

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 December 1984

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