Abstract
A VLSI VAX microcomputer, which implements the native VAX computer architecture and instruction set, uses 16K by 40 bits of ROM control store. To decrease the cost of making changes to released microcode, the hardware supports a patching mechanism whereby control flow can be switched between the read-only control memory and a smaller writable control memory. This paper describes the system design considerations that led to the development of the patchable control store, actual implementation of the control store, the effectiveness of the patching scheme, and its impact on system performance.
- 1 VAX Architecture Reference Manual. Revision 6.1. Digital Equipment Corp., Bedford. Mass., 1982.Google Scholar
- 2 W.J. Bauer et al., "Read-only Store Patching Methodology." IBM Tech Disel Bulietin. vol. 22, no. 1, pp. 350-2, June. 1979.Google Scholar
- 3 W.N. Johnson, "A VLSI VAX Chip Set," ISSCC Digest of Technical Papers. pp. 174- 175, 1984.Google Scholar
- 4 Dileep Bhandarkar. "Architecture Management for Ensuring Software Compatibility in the VAX Family of Computers," IEEE Computer, pp. 87-93. Feb., 1982.Google Scholar
- 5 D.W. Clark and H.M. Levy. "Measurement and Analysis of Instruction Use in the VAX-11/780." Proc. 9th Annual Symposium on Computer Architecture. vol. 10. no. 3, pp. 9-17. April. 1982. Google Scholar
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Patchable control store for reduced microcode risk in a VLSI VAX microcomputer
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Patchable control store for reduced microcode risk in a VLSI VAX microcomputer
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