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Compaction of two-level microprograms for a multiprocessor computer

Published:01 December 1984Publication History
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Abstract

An optimizing loader has been designed and developed for two-level microprograms of a multiprocessor computer. In the computer, a microinstruction activates nanoprograms in multiprocessors, specifying nanoprogram start address and the processors to be activated. This scheme allows the loader to utilize the same nanoprogram among several microinstructions, which activate it, and compact the nanoaddress space by nanocode movement. The experimental results show that (i) the nanoprogram sizes are reduced from 17.3 to 31.0 % and (ii) the effect of the reduction is proportional to the number of microinstructions.

References

  1. 1 Baba. T., Hashimoto, N., Yamazaki, K., and Okuda. K.: "Microprogramming Support System for a Two-Level Microprogrammed Computer MUNAP," Trans. IECE Japan, (Oct. 1982), pp. 1256-1272.Google ScholarGoogle Scholar
  2. 2 Baba. T., Ishikawa, K., and Okuda, K.: "A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions," IEEE Trans. Comput., (Dec. 1982), pp. 1142-1156.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3 Baba. T., Yamazaki, K., Hashimoto, N., Kanai. H., Okuda, K. and Hashimoto, K.: "Experimentation with a Two-Level Microprogrammed Multiprocessor Computer," Proc. MICRO-16, (Oct. 1983), pp. 47-54.Google ScholarGoogle Scholar
  4. 4 Frieder, G., and Miller. J.: "An Analysis of Code Density for the Two-Level Programmable Control of the Nanodata QM-1," Proc. MICRO-10, (1977). pp. 26-32. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5 Kartashev. S.P., and Kartashev S.I., Editor: "Special Issue of Supersystems for the 80's." Computer (Nov. 1980).Google ScholarGoogle Scholar
  6. 6 Rideout, D.J.: "Considerations for Local Compaction of Nanocode for the Nanodata QM-1," Proc. MICRO- 14, (1981), pp. 205-214. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7 Sano, T., Baba, T., Yamazaki, K., Suzuki, S., and Okuda, K.: Software Testing through Tagged Architecture," (tentative title in English), 28-th Annu. Conf. of Infor. Proc. Soci. of Japan, (March 1984), pp. 623-624.Google ScholarGoogle Scholar
  8. 8 Stritter, S.: "Microprogrammed Implementation of a Single Chip Microprocessor." Proc. MICRO-11, (1978), pp. 8-16. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9 Yamazaki, K., et al.: "Development of a System Description Language for a Two-Level Microprogrammed Computer MUNAP." Trans. IECE Japan, (Jan. 1984), pp. 149-156.Google ScholarGoogle Scholar

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  1. Compaction of two-level microprograms for a multiprocessor computer

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      • Published in

        cover image ACM SIGMICRO Newsletter
        ACM SIGMICRO Newsletter  Volume 15, Issue 4
        MICRO 17: Proceedings of the Seventeenth Annual Microprogramming Workshop
        Dec. 1984
        302 pages
        ISSN:1050-916X
        DOI:10.1145/384281
        Issue’s Table of Contents
        • cover image ACM Conferences
          MICRO 17: Proceedings of the 17th annual workshop on Microprogramming
          December 1984
          325 pages

        Copyright © 1984 Authors

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 1 December 1984

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