Abstract
A modified version of D. Warren's sequential Prolog machine architecture is described. Data and instruction formats are given. A microcoded host architecture is also described, with formats and examples presented.
- 1 D. H. D. Warren, "An Abstract Prolog Instruction Set," Tech. report 309, Artificial Intelligence Center, SRI International, 1983.Google Scholar
- 2 E. Tick and D. H. D. Warren, "Towards a Pipelined Prolog Processor," 1984 International Symposium on Logic Programming, IEEE Computer Society, February 1984.Google Scholar
- 3 S. Wakefield, "Studies in Execution Architectures," Technical Report 237, Computer Systems Laboratory, Stanford University, 1983.Google Scholar
- 4 E. Tick, "Towards a Multiple Pipeline Prolog Processor," International Workshop on High-Level Computer Architecture, The University of Maryland, May 1984.Google Scholar
Index Terms
Sequential Prolog machine: Image and host architectures
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