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Sequential Prolog machine: Image and host architectures

Published:01 December 1984Publication History
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Abstract

A modified version of D. Warren's sequential Prolog machine architecture is described. Data and instruction formats are given. A microcoded host architecture is also described, with formats and examples presented.

References

  1. 1 D. H. D. Warren, "An Abstract Prolog Instruction Set," Tech. report 309, Artificial Intelligence Center, SRI International, 1983.Google ScholarGoogle Scholar
  2. 2 E. Tick and D. H. D. Warren, "Towards a Pipelined Prolog Processor," 1984 International Symposium on Logic Programming, IEEE Computer Society, February 1984.Google ScholarGoogle Scholar
  3. 3 S. Wakefield, "Studies in Execution Architectures," Technical Report 237, Computer Systems Laboratory, Stanford University, 1983.Google ScholarGoogle Scholar
  4. 4 E. Tick, "Towards a Multiple Pipeline Prolog Processor," International Workshop on High-Level Computer Architecture, The University of Maryland, May 1984.Google ScholarGoogle Scholar

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  1. Sequential Prolog machine: Image and host architectures

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          cover image ACM SIGMICRO Newsletter
          ACM SIGMICRO Newsletter  Volume 15, Issue 4
          MICRO 17: Proceedings of the Seventeenth Annual Microprogramming Workshop
          Dec. 1984
          302 pages
          ISSN:1050-916X
          DOI:10.1145/384281
          Issue’s Table of Contents
          • cover image ACM Conferences
            MICRO 17: Proceedings of the 17th annual workshop on Microprogramming
            December 1984
            325 pages

          Copyright © 1984 Author

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 1 December 1984

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