Tian Bu
Lixin Gao
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On routing table growth
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Novel full-chip gridless routing considering double-via insertion
DAC '06: Proceedings of the 43rd annual Design Automation ConferenceAs the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via ...
A Multithreaded Initial Detailed Routing Algorithm Considering Global Routing Guides
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)Detailed routing is the most complicated and time-consuming stage in VLSI design and has become a critical process for advanced node enablement. To handle the high complexity of modern detailed routing, initial detailed routing is often employed to ...
RDL pre-assignment routing for flip-chip designs
GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSIBased on the concept of net renumbering and recovery to simplify the complexity of the global and detailed routing, an efficient RDL pre-assignment routing algorithm is proposed to maximize the number of routed nets with the minimization of total ...
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