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A compilation technique for software pipelining of loops with conditional jumps

Published:01 September 1988Publication History
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Abstract

We describe a compilation algorithm for efficient software pipelining of general inner loops, where the number of iterations and the time taken by each iteration may be unpredictable, due to arbitrary if-then-else statements and conditional exit statements within the loop. As our target machine, we assume a wide instruction word architecture that allows multi-way branching in the form of if-then-else trees, and that allows conditional register transfers depending on where the microinstruction branches to (a hardware implementation proposal for such a machine is briefly described in the paper). Our compilation algorithm, which we call the pipeline scheduling technique, produces a software-pipelined version of a given inner loop, which allows a new iteration of the loop to begin on every cycle whenever dependences and resources permit. The correctness and termination properties of the algorithm are studied in the paper.

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            cover image ACM SIGMICRO Newsletter
            ACM SIGMICRO Newsletter  Volume 19, Issue 3
            Sept. 1988
            58 pages
            ISSN:1050-916X
            DOI:10.1145/62185
            Issue’s Table of Contents

            Copyright © 1988 Author

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            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 1 September 1988

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