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The instruction parsing microarchitecture of CVAX microprocessor

Published:01 September 1988Publication History
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Abstract

CVAX is a single chip, CMOS VLSI VAX microprocessor. Several microarchitectural innovations helped achieve the desired performance goal of this machine. In particular, the instruction parsing and prefetching mechanism is different from other VAX implementations. This new instruction parsing microarchitecture is discussed in this paper.

References

  1. Supnik, R., "Micro VAX 32, a 32 Bit Microprocessor", IEEE Journal of Solid-State Circuits, Vol. SC-19, no. 5, October 1984.Google ScholarGoogle Scholar
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  5. Edward J. McLellan, et al, "The CVAX FPU, A CMOS VAX Floating Point Unit", to be presented at the International Conference on Computer Design, October, 1987.Google ScholarGoogle Scholar
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  7. David Archer, et al, "A 32b CMOS Microprocessor with On-Chip Instruction and Data Caching and Memory Management", ISSCC Digest of Technical Papers, Vol. 30, Coral Gables, FL, 1987.Google ScholarGoogle Scholar

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  1. The instruction parsing microarchitecture of CVAX microprocessor

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        • Published in

          cover image ACM SIGMICRO Newsletter
          ACM SIGMICRO Newsletter  Volume 19, Issue 3
          Sept. 1988
          58 pages
          ISSN:1050-916X
          DOI:10.1145/62185
          Issue’s Table of Contents

          Copyright © 1988 Author

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 1 September 1988

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