Abstract
HPSm is a single-chip microarchitecture designed and implemented at the University of California to achieve high performance. The approach is to exploit both vertical and horizontal concurracy in the microarchitecture. Experiments have been conducted to demonstrate the effectivenese of HPSm as compared is a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both central intensive and hosting point intensive benchmarks. For both types of benchmarks, we show that the HPSm microarchitecture achieves significant speedup ever the RISC/SPUR microarchitecture implemented with the same fabrication technology.
- Hwu, W. W. and Patt, Y. N., "HPSm. a High Performance Restricted Data Flow Architecture Having Minimal Functionality," The 13th International Symposium on Computer Architecture Conference Proceedings, pp. 297--306. Tokyo, Japan, June 1986. Google Scholar
Digital Library
- Hwu, W. W. and Patt, Y.N., "Design Choices for the HPSm Microprocessor Chip." Proceedings of the 20th Annual HICSS, pp. 329--336. Jan. 1987.Google Scholar
- Patt, Y. N., Hwu, W., and Shebanow, M.C., HPS, A New Microarchitecture: Rationale and Introduction" Proceedings of the 18th International Microprogramming Workshop, Asilomar, CA, December, 1985. Google Scholar
Digital Library
- Fisher, J. A., "Very Long Instruction Word Architecture and the ELI-512," research report YALEU/DCS/RR253, Yale University, Computer Science Department, April 1983.Google Scholar
- Anderson, D. W., Sparacio, F. J., Tomasulo. R. M., "The IBM System/360 Model 91: Machine Philosophy and Instruction - Handling," IBM Journal of Research and Development, Vol. 11, No. 1, 1967, pp. 8--24.Google Scholar
Digital Library
- Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, vol. 11, January 1967, pp 25--33.Google Scholar
Digital Library
- Jeong, D. K., "Design of PLL-Based Clock Generation Circuits," IEEE J. Solid State Circuits, vol. SC-22, no.2, pp. 255--261, April 1987.Google Scholar
Cross Ref
- Shebanow, M. C., Patt, Y. N., Hwu, W., and Melvin, S.W., "A C Compiler for HPS 1, Highly Parallel Execution Engine", Hawaii International Conference on System Sciences - 19, Honolulu, HI, January, 1986.Google Scholar
- Katevenis, M. C. H., Reduced Instruction Set Computers Architectures for VLSI, Ph.D. dissertation, Computer Science Division, University of California, Berkeley, Oct. 1983. {10} Hill, M.D., et al, "SPUR: A VLSI Multiprocessor Workstation," IEEE Computer, vol. 19, no. 11, pp. 8--22, November 1986.Google Scholar
- Hill, M. D., private communication, April 1987.Google Scholar
Index Terms
Exploiting horizontal and vertical concurrency via the HPSm microprocessor
Recommendations
Exploiting horizontal and vertical concurrency via the HPSm microprocessor
MICRO 20: Proceedings of the 20th annual workshop on MicroprogrammingHPSm is a single-chip microarchitecture designed and implemented at the University of California to achieve high performance. The approach is to exploit both vertical and horizontal concurrency in the microarchitecture. Experiments have been conducted ...
Exploiting Java instruction/thread level parallelism with horizontal multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the ...
Exploiting Java instruction/thread level parallelism with horizontal multithreading
ACSAC '01: Proceedings of the 6th Australasian conference on Computer systems architectureJava bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the ...






Comments