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Exploiting horizontal and vertical concurrency via the HPSm microprocessor

Published:01 September 1988Publication History
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Abstract

HPSm is a single-chip microarchitecture designed and implemented at the University of California to achieve high performance. The approach is to exploit both vertical and horizontal concurracy in the microarchitecture. Experiments have been conducted to demonstrate the effectivenese of HPSm as compared is a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both central intensive and hosting point intensive benchmarks. For both types of benchmarks, we show that the HPSm microarchitecture achieves significant speedup ever the RISC/SPUR microarchitecture implemented with the same fabrication technology.

References

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 19, Issue 3
              Sept. 1988
              58 pages
              ISSN:1050-916X
              DOI:10.1145/62185
              Issue’s Table of Contents

              Copyright © 1988 Authors

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 September 1988

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