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On tuning the microarchitecture of an HPS implementation of the VAX

Published:01 September 1988Publication History
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Abstract

The HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we describe our first full simulation of the micro VAX subset, and report the results of varying (i.e. tuning) certain important parameters.

References

  1. Anderson, D. W., F. J. Sparacia, and R. M. Tomasulo "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling," IBM J. of R & D, vol. 11, no 1, 1967.Google ScholarGoogle Scholar
  2. Arviad and K. P. Gostelow, "A New Interpreter for Dataflow and Its Implications for Computer Architecture," Department of Information and Computer Science, University of California, Irvine, Tech Report 72, October 1975.Google ScholarGoogle Scholar
  3. Deasis, J. B., and D. P. Misusas, "A Preliminary Architecture for a Basic Data Flow Processor," Proceedings of the Second International Symposium on Computer Architecture, 1975, pp. 126--132. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Hwu, W., S. Melvia, M.C. Shebasow, C. Chea, J. Wei and Y.N. Pall, "An HPS Implementation of the VAX; Initial Design and Analysis," Proceedings of the 19th Annual Hewai International Conference on System Sciences, 1966.Google ScholarGoogle Scholar
  5. Hwu Wea-mei, and Yale N. Patt, "Checkpoint Repair for High Performance Out-of-order Execution Machines," Proc. 14th Int. Symp. on Comp. Arch., June 2--5, 1987, Pittsburgh, Pa. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Patt, Y.N., Wea-mei Hwu, "HPS, a New Microarchitecture: Rationale and Introduction," Proc. of the 19th Microprogramming Workshop, Asilomar, California, Dec. 1965.Google ScholarGoogle Scholar
  7. Patt, Y. N., S. Melvin, W. Hwu, M. C. Shebasow, C. Cheu, J. Wei, "Run-Time Generation of HPS Microinstructions From a VAX Instruction Stream," Proceedings to the 19th Annual Workshop on Microprogramming, October 15--17, 1986, New York, New York. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Tomasulo R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. of R & D, vol. 11, no. 1967, pp 25 -- 33.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Swensea John, "High-Bandwidth/Low-Latercy Temporary Storage for Supercomputers," PhD Thesis, U.C. Berkeley, Nov., 1987. Google ScholarGoogle ScholarDigital LibraryDigital Library

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          cover image ACM SIGMICRO Newsletter
          ACM SIGMICRO Newsletter  Volume 19, Issue 3
          Sept. 1988
          58 pages
          ISSN:1050-916X
          DOI:10.1145/62185
          Issue’s Table of Contents

          Copyright © 1988 Authors

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 1 September 1988

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