Abstract
The HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we describe our first full simulation of the micro VAX subset, and report the results of varying (i.e. tuning) certain important parameters.
- Anderson, D. W., F. J. Sparacia, and R. M. Tomasulo "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling," IBM J. of R & D, vol. 11, no 1, 1967.Google Scholar
- Arviad and K. P. Gostelow, "A New Interpreter for Dataflow and Its Implications for Computer Architecture," Department of Information and Computer Science, University of California, Irvine, Tech Report 72, October 1975.Google Scholar
- Deasis, J. B., and D. P. Misusas, "A Preliminary Architecture for a Basic Data Flow Processor," Proceedings of the Second International Symposium on Computer Architecture, 1975, pp. 126--132. Google Scholar
Digital Library
- Hwu, W., S. Melvia, M.C. Shebasow, C. Chea, J. Wei and Y.N. Pall, "An HPS Implementation of the VAX; Initial Design and Analysis," Proceedings of the 19th Annual Hewai International Conference on System Sciences, 1966.Google Scholar
- Hwu Wea-mei, and Yale N. Patt, "Checkpoint Repair for High Performance Out-of-order Execution Machines," Proc. 14th Int. Symp. on Comp. Arch., June 2--5, 1987, Pittsburgh, Pa. Google Scholar
Digital Library
- Patt, Y.N., Wea-mei Hwu, "HPS, a New Microarchitecture: Rationale and Introduction," Proc. of the 19th Microprogramming Workshop, Asilomar, California, Dec. 1965.Google Scholar
- Patt, Y. N., S. Melvin, W. Hwu, M. C. Shebasow, C. Cheu, J. Wei, "Run-Time Generation of HPS Microinstructions From a VAX Instruction Stream," Proceedings to the 19th Annual Workshop on Microprogramming, October 15--17, 1986, New York, New York. Google Scholar
Digital Library
- Tomasulo R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. of R & D, vol. 11, no. 1967, pp 25 -- 33.Google Scholar
Digital Library
- Swensea John, "High-Bandwidth/Low-Latercy Temporary Storage for Supercomputers," PhD Thesis, U.C. Berkeley, Nov., 1987. Google Scholar
Digital Library
Index Terms
On tuning the microarchitecture of an HPS implementation of the VAX
Recommendations
On tuning the microarchitecture of an HPS implementation of the VAX
MICRO 20: Proceedings of the 20th annual workshop on MicroprogrammingThe HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we ...
A chip set microarchitecture for a high-performance VAX implementation
MICRO 17: Proceedings of the Seventeenth Annual Microprogramming WorkshopFast virtual-address translation and instruction parsing are two hard problems of implementing many modern architectures, including the VAX computer architecture. Meeting the additional constraint of fitting a VAX 11/780-computer-speed implementation ...
A chip set microarchitecture for a high-performance VAX implementation
MICRO 17: Proceedings of the 17th annual workshop on MicroprogrammingFast virtual-address translation and instruction parsing are two hard problems of implementing many modern architectures, including the VAX computer architecture. Meeting the additional constraint of fitting a VAX 11/780-computer-speed implementation ...






Comments