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An algorithm for microcode compaction of VHDL behavioral descriptions

Published:01 June 1988Publication History
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Abstract

We present as algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.

References

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  1. An algorithm for microcode compaction of VHDL behavioral descriptions

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 19, Issue 1-2
              June 1988
              66 pages
              ISSN:1050-916X
              DOI:10.1145/62197
              Issue’s Table of Contents

              Copyright © 1988 Author

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 June 1988

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