Abstract
We discuss the integration of a trace scheduling optimizer into a retargetable optimizing microcode compiler that handles complex timing relations. The trace scheduler requires no special treatment when retargeting the compiler, being constructed from machine independent algorithms that extract target micro-architecture details from a machine description used by the other compiler processes. We focus on the machine independent basis of the trace scheduler and demonstrate it on a hypothetical micro-architecture.
- R. Aho, A. V. Sethi and J. D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, Reading, MA, 1986.]] Google Scholar
Digital Library
- V. B. Allan. A Critical Analysis of the Global Optimization Problem for Horizontal Microcode. PhD thesis, Computer Science Department, Colorado State University, Fort Collins, Colorado, 1986. Also available as technical report MAD-86-20, Firmware Engineering and Micro-Architecture Design Laboratory, Department of Computer Science, Colorado State University.]] Google Scholar
Digital Library
- V. H. Allan and R. A. Mueller. Microcode Compaction with General Synchronous Timing. IEEE Transactions on Software Engineering (Special Issue on Firmware Engineering), 1986. Submitted for publication.]] Google Scholar
Digital Library
- T. Baba and H. Hagiwara. The MPG System: A Machine-Independent Efficient Microprogram Generator. IEEE Transactions on Computers, C-30(6):373--395, June 1981.]]Google Scholar
- Pin Chen. Software Pipeline: A Code Optimization Technique to Improve the Efficiency of Array Processors. Master's thesis, Institute of North-Western Telecommunication Engineering, China, 1984.]]Google Scholar
- W. Damm. An Axiomatization of Low-Level Parallelism in Microarchitectures. In Proceedings of the 17th Microprogramming Workshop (MICRO-17), pages 314--323, New Orleans, LA, November 1984.]] Google Scholar
Digital Library
- W. Damm. Automatic Generation of Simulation Tools: A Case Study in the Design of a Retargetable Firmware Development System. In Advances in Microprocessing and Microprogramming, North-Holland, Amsterdam, Holland, 1984.]]Google Scholar
- W. Damm, G. Doehmen, K. Merkel, and M. Sichelschmidt. The AADL/S* Approach to Firmware Design Specification. IEEE Software, 3(4):27--37, July 1986.]]Google Scholar
Digital Library
- S. Dasgupta. A Model of Clorked Micro-Architectures for Firmware Engineering and Design Automation Applications. In Proceedings of the 17th Microprogramming Workshop (MICRO-17), pages 298--308, New Orleans, LA, November 1984.]] Google Scholar
Digital Library
- S. Dasgupta. Towards a Microprogramming Schema. In Proceedings of the 11th Microprogramming Workshop (MICRO-11), pages 144--153, Nov 1978.]] Google Scholar
Digital Library
- S. Dasgupta, P. A. Wilsey, and J. Heinanen. Axiomatic specifications in firmware development systems. IEEE Software, 3(4):49--58, July 1986.]]Google Scholar
Digital Library
- S. Davidson. A Survey of High-Level Languages for Microprogramming. In S. Habib and S. Dasgupta, editors, Handbook of Microprogramming and Firmware Engineering, Van Nostrand, New York, NY, 1986. Forthcoming.]]Google Scholar
- S. Davidson. Design and Construction of a Virtual Machine Resource Binding Language. PhD thesis, Computer Science Department, University of South-western Louisiana, Lafayette, LA, 1980.]] Google Scholar
Digital Library
- J. R. Ellis. Bulldog: A Compiler for VLIW Architectures. The MIT Press, 1985. PhD thesis, Yale, 1984.]] Google Scholar
Digital Library
- J. A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, C-30(7):478--490, July 1981.]]Google Scholar
Digital Library
- M. Ganapathi. Retargetable Code Generation and Optimization Using Attribute Grammars. PhD thesis, Computer Science Department, University of Wisconsin, Madison, WI, 1980.]] Google Scholar
Digital Library
- R. P. Gurd. Experience Developing Microcode Using a High Level Language. In Proceedings of the 16th Microprogramming Workshop (MICRO-16), pages 179--184, Downingtown, PA, Oct 1983.]]Google Scholar
Digital Library
- S. Isoda, Y. Kobayashi, and T. Ishida. Global Compaction of Horizontal Microprograms Based on the Generalized Data Dependency Graph. IEEE Transactions on Computers, C-32(10):922--933, October 1983.]]Google Scholar
Digital Library
- D. Landskov, S. Davidson, B. D. Shriver, and P. W. Mallett. Local Microcode Compaction Techniques. ACM Computing Surveys, 12(3):261--294, September 1980.]] Google Scholar
Digital Library
- J. L. Linn. SRDAG Compaction: A Generalization of Trace Scheduling to Increase the Use of Global Context Information. In Proceedings of the 16th Microprogramming Workshop (MICRO-16), pages 11--22, Downingtown, PA, October 1983.]]Google Scholar
- P. Marwedel. A Retargetable Compiler for a High-Level Microprogramming Language. In Proceedings of the 17th Microprogramming Workshop (MICRO-17), pages 267--274, New Orleans, LA, Nov 1984.]] Google Scholar
Digital Library
- R. A. Mueller and P. H. Sweany. Horizon Code Generator Series-Parallel DDG Coupler/Decoupler (Version 3.1). Technical Report MAD-86-10, Firmware Engineering and Micro-Architecture Design Laboratory, Colorado State University, Fort Collins, CO, September 1986.]]Google Scholar
- B. L. Plomondon, M. R. Duda, and R. A. Mueller. Horizon Compiler Am29500 FFT Micro-Architecture 1. Technical Report MAD-86-16, Firmware Engineering and Micro-Architecture Design Laboratory, Colorado State University, Fort Collins, CO, September 1986.]]Google Scholar
- B. Su, S. Ding, and L. Jin. An improvement of trace scheduling for global microcode compaction. In Proceedings of the 17th Microprogramming Workshop (MICRO-17), pages 78--85, New Orleans, LA, Nov 1984.]] Google Scholar
Digital Library
- B. Su, S. Ding, and J. Xia. URPR - An extension of URCR for Software Pipelining. In Proceedings of the 19th Microprogramming Workshop (MICRO-19), pages 94--103, New York, NY, December 1986.]] Google Scholar
Digital Library
- S. R. Vegdahl. Local Code Generation and Compaction in Optimizing Microcode Compilers. PhD thesis, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA, 1982.]] Google Scholar
Digital Library
Index Terms
Trace scheduling optimization in a retargetable microcode compiler
Recommendations
Trace scheduling optimization in a retargetable microcode compiler
MICRO 20: Proceedings of the 20th annual workshop on MicroprogrammingWe discuss the integration of a trace scheduling optimizer into a retargetable optimizing microcode compiler that handles complex timing relations. The trace scheduler requires no special treatment when retargeting the compiler, being constructed from ...
A VLIW architecture for a trace Scheduling Compiler
Special issue on architectural support for programming languages and operating systemsA VLIW (very long instruction word) architecture machine called the TRACE has been built along with its companion Trace Scheduling compacting compiler. This machine has three hardware configurations, capable of executing 7, 14, or 28 operations ...






Comments