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Design and performance measurements of a parallel machine for the unification algorithm

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Published:01 August 1989Publication History
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Abstract

Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up the unification algorithm. The machine is simulated at the register transfer level and the simulation results as well as performance comparison with a serial unification coprocessor are presented.

References

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 20, Issue 3
              Sep. 1989
              253 pages
              ISSN:1050-916X
              DOI:10.1145/75395
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 22: Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
                August 1989
                253 pages
                ISBN:0897913248
                DOI:10.1145/75362

              Copyright © 1989 Authors

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              Association for Computing Machinery

              New York, NY, United States

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              • Published: 1 August 1989

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