Abstract
Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up the unification algorithm. The machine is simulated at the register transfer level and the simulation results as well as performance comparison with a serial unification coprocessor are presented.
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Cross Ref
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Index Terms
Design and performance measurements of a parallel machine for the unification algorithm
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Design and performance measurements of a parallel machine for the unification algorithm
MICRO 22: Proceedings of the 22nd annual workshop on Microprogramming and microarchitectureUnification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up ...
Ramified Higher-Order Unification
LICS '97: Proceedings of the 12th Annual IEEE Symposium on Logic in Computer ScienceWhile unification in the simple theory of types (a.k.a. higher-order logic) is undecidable, we show that unification in the pure ramified theory of types with integer levels is decidable. Since pure ramified type theory is not very expressive, we ...






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