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On reordering instruction streams for pipelined computers

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Published:01 August 1989Publication History
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Abstract

This paper describes a method to reorder the straight line instruction streams for pipelined computers which have one instruction issue unit but may contain multiple function units. The objective is to make the most efficient usage of the pipelines within the computer system. The input to the scheduler is the intermediate code of a compiler, and is represented by a data dependence graph (DDG).

The scheduler is a kind of list scheduler. The data dependence and the pipeline effect of the function units within the system have been considered for finding a most suitable time slot for each node during reordering time.

The scheduler has been implemented and several scientific application programs have been tested. The results show that in most of the cases the scheduler will achieve the optimal result. The average instruction issue rate is over 96%. As a comparison, the issue rate of an ordinary compiler is only 22%; and the issue rate of a compiler with the effect of pipeline but without reordering the instruction stream is about 45%.

References

  1. Aho-86 Aho, A. F., Sethi, R. and Ullman, J. D., Compilers: Principles, Techniques and Tools, Addison Wesley, 1986 Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Arya85 Arya, S." An Optimal Instruction - Scheduling Models for Class of Vectors Processor", IEEE Transactions on Computers, V-34(11), p981-995, Nov. 1985Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Ausl82 Auslander, M. and Hopkins, M.," An Overview of the PL.8 Compiler", Proc. of the SIGPLAN '82 Symposium on Compiler Construction, p22-31, Jun. 1982 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Brow84 Brownrigg, D. R. K.," The Weighted Median Filters,", CACM, V-27(8), p807-818, 1984 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Brun80 Bruno, J., Jones, J. W. and So, K.,' Deterministic Scheduling with Pipelined Processors", IEEE Transactions on Computers, C-29(4), p308 316, Apr. 1980Google ScholarGoogle Scholar
  6. Bucy80 Bucy, R. S. and Senne, K. D.," Nonlinear Filtering Algorithms for Vector Machines,", Computers and Mathematics, V-6(3), p317-338, 1980Google ScholarGoogle Scholar
  7. Burd85 Burden, R. L. and Faires, J. D., Numerical Analysis, Prindle, Weber and Schmidt, Boston, 1985Google ScholarGoogle Scholar
  8. Dong79 Dongarra, J. J. and Hinds, A. R.," Unrolling Loops in TORTRAN,", Software Praticce and Experience, V-9(3), Mar. 1979Google ScholarGoogle Scholar
  9. Elli86 Ellis, J. R., Bulldog: A Compiler for VLIW Architectures, The MIT Press Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Gibb86 Gibbons, P. B. and Muchnick, S. S.," Efficient Instruction Scheduling for a Pipelined Architecture", Proc. of the SIGPLAN '86 Symposium on Compiler Construction, p11-16, Jun. 1986 Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Gonz77 Gonzalez, M. J.,' Deterministic Processor Scheduling", ACM Computing Surveys, V-9(3), p173-204, Sep. 1977 Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Gros83 Gross, T. R., Code Optimization of Pipeline Constraints, Technique Report No. 255, Computer System Laboratory, Dept. of Electric Engineering and Conputer Science, Stanford University, Dec. 1983Google ScholarGoogle Scholar
  13. Henn83 Hennessy, J. and Gross Thomas," Postpass Code Optimization of Pipeline Constraints", ACM Transactions on Program.ming Language and Ststems, V-5(3), p422-448, Jul. 1983 Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. John86 Johnson, M. S. and Miller, T. C.," Effectiveness of a Machine Level Global Optimizer,", Proc. of the SIGPLAN '86 Symposium on Compiler Construction, p99-108, Jun. 1986 Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Kasa84 Kasahara, H. and Narita, S.,"" Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Proccessing", IEEE Transactions on Computers, C-33(11), p1023-1029, Nov. 1984Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Kate85 Katevenis, G. H., Reduced Instruction Set Computer Architecture for VLSI, The MIT Press, 1985 Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Kogg81 Kogge, P. M.", The Architecture of Pipelined Computers, Hemisphere Publishing Corporation, 1981Google ScholarGoogle Scholar
  18. Kuck81 Kuck, D. J. etc.," Dependence Graphs and Compiler Optimizations", ACM 8th Annual Symposium on Principles of Programming Languages, p207-218, Jan. 1981 Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Lawl87 Lawler, E., Lenstra, J. K., Martel, C. and Simons, B.," Pipeline Scheduling: A Survey", IBM Research Report, RJ5738 (57717), July 15, 1987Google ScholarGoogle Scholar
  20. Padu86 Padua, D. A. and Wolfe, M. J.," Advanced Compiler Optimizations for Supercomputers", Communicatipons of the ACM, V-29(12), p1184-1200, Dec. 1986 Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Poly88 Polychronopoulos, C. D., Parallel Progrumming and Compilers, Kluwer Academic Publishers, 1988 Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Rau-81 Rau, B. R. and Glaeser, C. D.," Some Scheduling Techniques and An Easily Schedulable Horizontal Architecture for High Performance Scientific computing", Proc. of 14th Annual Workshop on Microprogramming, p183-198, 1981 Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Rau-82 Rau, B. R., Glaeser, C. D., and Picard, R. L.," Efficient Code Generation for Horizontal Architecture: Compiler Techniques and Architecture Support", Proc. of the 9th Annual Inter. Symposium on Computer Architecture, p131-139, 1982 Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Ryma82 Rymarczyk, J. W.," Coding Guidelines for Pipelined Processors,", Proc. of the Symposium on Architecture Support for Programming Language and Operating System, p12-19, Mar. 1987 Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Sahn84 Sahni, S.," Scheduling Multipipeline and Multiprocessor Computers', IEEE Transactions on Computers, C-30(1), p637-645, Jul. 1984Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Shie89 Shieh, J. J. and Papachristou, C.," A Mapping Strategy for Multiprocessor Systems", To be published.Google ScholarGoogle Scholar
  27. Thom64 Thornton, J. E.," Parallel Operation in Control Data 6600,", Proc. of Fall Joint Computer Conference, Part 2, V-26, p33-40, 1964Google ScholarGoogle Scholar
  28. Toma67 Tomasulo, R. M., " An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, p25-33, Jan. 1967Google ScholarGoogle Scholar
  29. Wali87 Walicki, J. and Laughlin, J. ," Opera, tion Scheduling in Reconfigurable Multifunction Pipelines,", Proc. of 20th Annual Workshop on Microprogramming, p80-87, 1987 Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Wedi82 Wedig, R. G., Dynamic Detection of Concurrency in DEL Instruction Streams, Technique Report No. 231, Computer System Laboratory, Dept. of Electric Engineering and Conputer Science, Stanford University, Feb. 1982 Google ScholarGoogle ScholarDigital LibraryDigital Library

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        • Published in

          cover image ACM SIGMICRO Newsletter
          ACM SIGMICRO Newsletter  Volume 20, Issue 3
          Sep. 1989
          253 pages
          ISSN:1050-916X
          DOI:10.1145/75395
          Issue’s Table of Contents
          • cover image ACM Conferences
            MICRO 22: Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
            August 1989
            253 pages
            ISBN:0897913248
            DOI:10.1145/75362

          Copyright © 1989 Authors

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 1 August 1989

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