A multi-user data flow architecture

ABSTRACT

This paper discusses the design of a prototype data flow machine that has memory management hardware in each memory block. This facility allows loading and deleting code that is produced by independent compilations. The first sections of the paper deal with the general architecture of the machine and the format specifications for the instruction cells, logical addresses, and switch packets. The paper concludes with a discussion of the mapping hardware used in the memory blocks. The results of a simulation study for this subsystem are also presented.

References

1. 1.J. B. Dennis. First version of a data flow procedure language, Lecture Notes in Computer Science, 19 (Springer-Verlag: 1974), 362-376.
2. 2.J. B. Dennis, G. A. Boughton, and C. K. C. Leung. Building blocks for data flow prototypes, Proceedings of the 7th Annual Symposium on Computer Architecture (1980), 1-8.
3. 3.J. Gurd and I. Watson. Data driven systems for high speed parallel computing-Part I: Structuring software for parallel execution, Computer Design (June 1980), 91-106.
4. 4.F. J. Burkowski. Design aspects of a data flow processor (Technical report No. 3 of the Mandala Project, Department of Computer Science), University of Manitoba.
5. 5.E. Goto, T. Ida, and T. Gunji. Parallel hashing algorithms, Information Processing Letters, 6 (1977), 8-13.
6. 6.T. Ida and E. Goto. Performance of a parallel hash hardware with key deletion, Information Processing 77 (New York: North Holland, 1977), 643-647.

Index Terms

• Computer systems organization

  • Architectures

    • Other architectures

      • Data flow architectures

    • Parallel architectures

      • Very long instruction word

    • Serial architectures

      • Complex instruction set computing

      • Reduced instruction set computing

• Networks

  • Network types

    • Packet-switching networks