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Persistence semantics for weak memory: integrating epoch persistency with the TSO memory model

Published:24 October 2018Publication History
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Abstract

Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of volatile memory (RAM). To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the formal semantics of such persistency models in the context of existing mainstream hardware has been unexplored to date. To close this gap, we integrate the buffered epoch persistency model with the 'total-store-order' (TSO) memory model of the x86 and SPARC architectures. We thus develop the PTSO ('persistent' TSO) model and formalise its semantics both operationally and declaratively. We demonstrate that the two characterisations of PTSO are equivalent. We then formulate the notion of persistent linearisability to establish the correctness of library implementations in the context of persistent memory. To showcase our formalism, we develop two persistent implementations of a queue library, and apply persistent linearisability to show their correctness.

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References

  1. Hans-J. Boehm and Dhruva R. Chakrabarti. 2016. Persistence Programming Models for Non-volatile Memory. In Proceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management (ISMM 2016). ACM, New York, NY, USA, 55–67. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Dhruva R. Chakrabarti, Hans-J. Boehm, and Kumud Bhandari. 2014. Atlas: Leveraging Locks for Non-volatile Memory Consistency. SIGPLAN Not. 49, 10 (Oct. 2014), 433–452. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Andreas Chatzistergiou, Marcelo Cintra, and Stratis D. Viglas. 2015. REWIND: Recovery Write-ahead system for In-memory Non-volatile Data-structures. Proc. VLDB Endow. 8, 5 (Jan. 2015), 497–508. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Joel Coburn, Adrian M. Caulfield, Ameen Akel, Laura M. Grupp, Rajesh K. Gupta, Ranjit Jhala, and Steven Swanson. 2011. NV-Heaps: Making Persistent Objects Fast and Safe with Next-generation, Non-volatile Memories. SIGPLAN Not. 46, 3 (March 2011), 105–118. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Jeremy Condit, Edmund B. Nightingale, Christopher Frost, Engin Ipek, Benjamin Lee, Doug Burger, and Derrick Coetzee. 2009. Better I/O Through Byte-addressable, Persistent Memory. In Proceedings of the ACM SIGOPS 22Nd Symposium on Operating Systems Principles (SOSP ’09). ACM, New York, NY, USA, 133–146. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop Gupta, and John Hennessy. 1990. Memory Consistency and Event Ordering in Scalable Shared-memory Multiprocessors. SIGARCH Comput. Archit. News 18, 2SI (May 1990), 15–26. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Maurice P. Herlihy and Jeannette M. Wing. 1990. Linearizability: A Correctness Condition for Concurrent Objects. ACM Trans. Program. Lang. Syst. 12, 3 (July 1990), 463–492. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. IBM. 2013. IBM solidDB. (2013). https://www.ibm.com/support/knowledgecenter/en/SSPK3V_7.0.0/master/welcome.kc.htmlGoogle ScholarGoogle Scholar
  9. Intel. 2014. Intel architecture instruction set extensions programming reference. (2014). https://software.intel.com/sites/ default/files/managed/07/b7/319433- 023.pdfGoogle ScholarGoogle Scholar
  10. International technology roadmap for semiconductors. 2007. Process Integration, devices, and structures. (2007). http: //www.maltiel- consulting.com/ITRS_2011- Process- Integration- Devices- Structures.pdfGoogle ScholarGoogle Scholar
  11. Joseph Izraelevitz, Terence Kelly, and Aasheesh Kolli. 2016a. Failure-Atomic Persistent Memory Updates via JUSTDO Logging. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’16). ACM, New York, NY, USA, 427–442. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Joseph Izraelevitz, Hammurabi Mendes, and Michael L. Scott. 2016b. Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model. In Distributed Computing, Cyril Gavoille and David Ilcinkas (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 313–327.Google ScholarGoogle Scholar
  13. Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, and Stratis Viglas. 2015. Efficient Persist Barriers for Multicores. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 660–671. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. T. Kawahara, K. Ito, R. Takemura, and H. Ohno. 2012. Spin-transfer torque RAM technology: Review and prospect. Microelectronics Reliability 52, 4 (2012), 613 – 627.Google ScholarGoogle ScholarCross RefCross Ref
  15. Aasheesh Kolli, Steven Pelley, Ali Saidi, Peter M. Chen, and Thomas F. Wenisch. 2016a. High-Performance Transactions for Persistent Memories. SIGPLAN Not. 51, 4 (March 2016), 399–411.Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, and Thomas F. Wenisch. 2016b. Delegated Persist Ordering. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 58, 13 pages. http://dl.acm.org/citation.cfm?id=3195638.3195709 Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting Phase Change Memory As a Scalable Dram Alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA ’09). ACM, New York, NY, USA, 2–13. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Maged M. Michael and Michael L. Scott. 1996. Simple, Fast, and Practical Non-blocking and Blocking Concurrent Queue Algorithms. In Proceedings of the Fifteenth Annual ACM Symposium on Principles of Distributed Computing (PODC ’96). ACM, New York, NY, USA, 267–275. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Faisal Nawab, Joseph Izraelevitz, Terence Kelly, Charles B. Morrey, Dhruva R. Chakrabarti, and Michael James Scott. 2017. Dalí: A Periodically Persistent Hash Map. In DISC.Google ScholarGoogle Scholar
  20. Scott Owens. 2010. Reasoning About the Implementation of Concurrency Abstractions on x86-TSO. In Proceedings of the 24th European Conference on Object-oriented Programming (ECOOP’10). Springer-Verlag, Berlin, Heidelberg, 478–503. http://dl.acm.org/citation.cfm?id=1883978.1884011 Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Steven Pelley, Peter M. Chen, and Thomas F. Wenisch. 2014. Memory Persistency. In Proceeding of the 41st Annual International Symposium on Computer Architecuture (ISCA ’14). IEEE Press, Piscataway, NJ, USA, 265–276. http: //dl.acm.org/citation.cfm?id=2665671.2665712 Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Christopher Pulte, Shaked Flur, Will Deacon, Jon French, Susmit Sarkar, and Peter Sewell. 2017. Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8. Proc. ACM Program. Lang. 2, POPL, Article 19 (Dec. 2017), 29 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Azalea Raad and Viktor Vafeiadis. 2018. Technical Appendix. (2018). http://plv.mpi- sws.org/ptso/Google ScholarGoogle Scholar
  24. Peter Sewell, Susmit Sarkar, Scott Owens, Francesco Zappa Nardelli, and Magnus O. Myreen. 2010. X86-TSO: A Rigorous and Usable Programmer’s Model for x86 Multiprocessors. Commun. ACM 53, 7 (July 2010), 89–97. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. SPARC. 1992. The SPARC Architecture Manual: Version 8. Prentice-Hall, Inc., Upper Saddle River, NJ, USA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams. 2008. The missing memristor found. Nature 453 (2008), 80 – 83.Google ScholarGoogle ScholarCross RefCross Ref
  27. TimesTen Team. 1999. In-memory Data Management for Consumer Transactions the Timesten Approach. SIGMOD Rec. 28, 2 (June 1999), 528–529. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Viktor Vafeiadis and Chinmay Narayan. 2013. Relaxed Separation Logic: A Program Logic for C11 Concurrency. In Proceedings of the 2013 ACM SIGPLAN International Conference on Object Oriented Programming Systems Languages & Applications. 867–884. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Haris Volos, Andres Jaan Tack, and Michael M. Swift. 2011. Mnemosyne: Lightweight Persistent Memory. SIGPLAN Not. 47, 4 (March 2011), 91–104. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Zhaoguo Wang, Hao Qian, Jinyang Li, and Haibo Chen. 2014. Using Restricted Transactional Memory to Build a Scalable In-memory Database. In Proceedings of the Ninth European Conference on Computer Systems (EuroSys ’14). ACM, New York, NY, USA, Article 26, 15 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Xiaojian Wu and A. L. Narasimha Reddy. 2011. SCMFS: A File System for Storage Class Memory. In Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC ’11). ACM, New York, NY, USA, Article 39, 11 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, and Norman P. Jouppi. 2013. Kiln: Closing the Performance Gap Between Systems with and Without Persistence Support. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 421–432. Google ScholarGoogle ScholarDigital LibraryDigital Library

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